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[Valgrind-developers] [valgrind] mips64: use register numbers
instead of aliases for inline assembly
From: Petar J. <pe...@so...> - 2018-04-04 09:53:38
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e14452877f502152b736ba9281658fb35355c842 commit e14452877f502152b736ba9281658fb35355c842 Author: Petar Jovanovic <mip...@gm...> Date: Wed Apr 4 11:51:05 2018 +0200 mips64: use register numbers instead of aliases for inline assembly There is an inconsistency in MIPS tools for N32/N64 related to register aliases. To avoid ambiguity, use register numbers instead of aliases where needed. Diff: --- VEX/priv/guest_mips_helpers.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c index 4f74593..af047ad 100644 --- a/VEX/priv/guest_mips_helpers.c +++ b/VEX/priv/guest_mips_helpers.c @@ -484,47 +484,47 @@ HWord mips_dirtyhelper_rdhwr ( UInt rd ) #define ASM_VOLATILE_UNARY32(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %2, $31" "\n\t" \ "mtc1 %1, $f20" "\n\t" \ #inst" $f20, $f20" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (loFsVal), "r" (fcsr) \ - : "t0", "$f20" \ + : "$8", "$f20" \ ); #define ASM_VOLATILE_UNARY32_DOUBLE(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %2, $31" "\n\t" \ "ldc1 $f20, 0(%1)" "\n\t" \ #inst" $f20, $f20" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&fsVal), "r" (fcsr) \ - : "t0", "$f20", "$f21" \ + : "$8", "$f20", "$f21" \ ); #define ASM_VOLATILE_UNARY64(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ ".set fp=64" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %2, $31" "\n\t" \ "ldc1 $f24, 0(%1)" "\n\t" \ #inst" $f24, $f24" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&(addr[fs])), "r" (fcsr) \ - : "t0", "$f24" \ + : "$8", "$f24" \ ); #define ASM_VOLATILE_MSA_UNARY(inst) \ @@ -549,49 +549,49 @@ HWord mips_dirtyhelper_rdhwr ( UInt rd ) #define ASM_VOLATILE_BINARY32(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %3, $31" "\n\t" \ "mtc1 %1, $f20" "\n\t" \ "mtc1 %2, $f22" "\n\t" \ #inst" $f20, $f20, $f22" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (loFsVal), "r" (loFtVal), "r" (fcsr) \ - : "t0", "$f20", "$f22" \ + : "$8", "$f20", "$f22" \ ); #define ASM_VOLATILE_BINARY32_DOUBLE(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %3, $31" "\n\t" \ "ldc1 $f20, 0(%1)" "\n\t" \ "ldc1 $f22, 0(%2)" "\n\t" \ #inst" $f20, $f20, $f22" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&fsVal), "r" (&ftVal), "r" (fcsr) \ - : "t0", "$f20", "$f21", "$f22", "$f23" \ + : "$8", "$f20", "$f21", "$f22", "$f23" \ ); #define ASM_VOLATILE_BINARY64(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %3, $31" "\n\t" \ "ldc1 $f24, 0(%1)" "\n\t" \ "ldc1 $f26, 0(%2)" "\n\t" \ #inst" $f24, $f24, $f26" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&(addr[fs])), "r" (&(addr[ft])), "r" (fcsr) \ - : "t0", "$f24", "$f26" \ + : "$8", "$f24", "$f26" \ ); #define ASM_VOLATILE_MSA_BINARY(inst) \ |
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From: John R. <jr...@bi...> - 2018-04-04 16:11:37
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> mips64: use register numbers instead of aliases for inline assembly > > There is an inconsistency in MIPS tools for N32/N64 related to register > aliases. To avoid ambiguity, use register numbers instead of aliases where > needed. Please give URLs or other citations to the differing definitions of t0, and also an explanation if you can. There may be other places that suffer. |
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From: Petar J. <mip...@gm...> - 2018-04-05 17:05:40
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On Wed, Apr 4, 2018 at 6:11 PM, John Reiser <jr...@bi...> wrote: >> mips64: use register numbers instead of aliases for inline assembly >> There is an inconsistency in MIPS tools for N32/N64 related to >> register >> aliases. To avoid ambiguity, use register numbers instead of aliases >> where >> needed. > > > Please give URLs or other citations to the differing definitions of t0, > and also an explanation if you can. There may be other places that suffer. > > In short, in MIPS, registers $8-$11 and $12-$15 have different aliases based on the ABI. There is also a mismatch between documents that describe them (in SGI documentation, there are no t0-t3 in N32/64, but these aliases exist for N32/64 in MD00305). Regards, Petar |