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From: Philippe W. <phi...@so...> - 2017-09-19 21:15:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=92ec6d08bbe3e06e76b13373ff31ff81d94550b7 commit 92ec6d08bbe3e06e76b13373ff31ff81d94550b7 Author: Philippe Waroquiers <phi...@sk...> Date: Tue Sep 19 23:12:35 2017 +0200 Fix assert on ppc32 due to typo for GPR28 The below commit introduced a regression on ppc32 ommit 00d4667295a821fef9eb198abcb0c942dffb6045 Author: Ivo Raisr <iv...@iv...> Date: Wed Sep 6 08:10:36 2017 +0200 Reorder allocatable registers for AMD64, X86, and PPC so that the callee saved are listed first. Helper calls always trash all caller saved registers. By listing the callee saved first then VEX register allocator (both v2 and v3) is more likely to pick them and does not need to spill that much before helper calls. Investigation/fix done by Ivo. Diff: --- VEX/priv/host_ppc_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index 8ee789a..27b3b38 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -71,7 +71,7 @@ ST_IN HReg hregPPC_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 10, 10); } ST_IN HReg hregPPC_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 11, 11); } ST_IN HReg hregPPC_GPR26 ( Bool mode64 ) { return GPR(mode64, 26, 12, 12); } ST_IN HReg hregPPC_GPR27 ( Bool mode64 ) { return GPR(mode64, 27, 13, 13); } -ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28, 14, 44); } +ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28, 14, 14); } ST_IN HReg hregPPC_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 15, 15); } ST_IN HReg hregPPC_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 16, 16); } |