|
From: Ivo R. <ir...@so...> - 2017-08-15 09:54:10
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=9dc0cf76da351a95745132440437bceb76c6d356 commit 9dc0cf76da351a95745132440437bceb76c6d356 Author: Ivo Raisr <iv...@iv...> Date: Tue Aug 8 07:03:04 2017 +0200 Introduce HInstrSB into VEX backend headers. Diff: --- VEX/priv/host_amd64_defs.h | 2 +- VEX/priv/host_arm64_defs.h | 2 +- VEX/priv/host_arm_defs.h | 2 +- VEX/priv/host_mips_defs.h | 2 +- VEX/priv/host_ppc_defs.h | 2 +- VEX/priv/host_s390_defs.h | 2 +- VEX/priv/host_x86_defs.c | 23 +++++++++++++++++++++++ VEX/priv/host_x86_defs.h | 11 +++++++++-- 8 files changed, 38 insertions(+), 8 deletions(-) diff --git a/VEX/priv/host_amd64_defs.h b/VEX/priv/host_amd64_defs.h index 39682ef..e41fe34 100644 --- a/VEX/priv/host_amd64_defs.h +++ b/VEX/priv/host_amd64_defs.h @@ -807,7 +807,7 @@ extern AMD64Instr* directReload_AMD64 ( AMD64Instr* i, extern const RRegUniverse* getRRegUniverse_AMD64 ( void ); -extern HInstrArray* iselSB_AMD64 ( const IRSB*, +extern HInstrSB* iselSB_AMD64 ( const IRSB*, VexArch, const VexArchInfo*, const VexAbiInfo*, diff --git a/VEX/priv/host_arm64_defs.h b/VEX/priv/host_arm64_defs.h index 14b2de6..bbc211d 100644 --- a/VEX/priv/host_arm64_defs.h +++ b/VEX/priv/host_arm64_defs.h @@ -1010,7 +1010,7 @@ extern void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, extern const RRegUniverse* getRRegUniverse_ARM64 ( void ); -extern HInstrArray* iselSB_ARM64 ( const IRSB*, +extern HInstrSB* iselSB_ARM64 ( const IRSB*, VexArch, const VexArchInfo*, const VexAbiInfo*, diff --git a/VEX/priv/host_arm_defs.h b/VEX/priv/host_arm_defs.h index e8a2eb7..19c4299 100644 --- a/VEX/priv/host_arm_defs.h +++ b/VEX/priv/host_arm_defs.h @@ -1073,7 +1073,7 @@ extern void genReload_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, extern const RRegUniverse* getRRegUniverse_ARM ( void ); -extern HInstrArray* iselSB_ARM ( const IRSB*, +extern HInstrSB* iselSB_ARM ( const IRSB*, VexArch, const VexArchInfo*, const VexAbiInfo*, diff --git a/VEX/priv/host_mips_defs.h b/VEX/priv/host_mips_defs.h index 481a487..11bea76 100644 --- a/VEX/priv/host_mips_defs.h +++ b/VEX/priv/host_mips_defs.h @@ -703,7 +703,7 @@ extern void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, extern const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 ); -extern HInstrArray *iselSB_MIPS ( const IRSB*, +extern HInstrSB *iselSB_MIPS ( const IRSB*, VexArch, const VexArchInfo*, const VexAbiInfo*, diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index 62c15ae..9a9187d 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -1218,7 +1218,7 @@ extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 ); -extern HInstrArray* iselSB_PPC ( const IRSB*, +extern HInstrSB* iselSB_PPC ( const IRSB*, VexArch, const VexArchInfo*, const VexAbiInfo*, diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h index 2026900..75a0a44 100644 --- a/VEX/priv/host_s390_defs.h +++ b/VEX/priv/host_s390_defs.h @@ -749,7 +749,7 @@ Int emit_S390Instr ( Bool *, UChar *, Int, const s390_insn *, Bool, const RRegUniverse *getRRegUniverse_S390( void ); void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); -HInstrArray *iselSB_S390 ( const IRSB *, VexArch, const VexArchInfo *, +HInstrSB *iselSB_S390 ( const IRSB *, VexArch, const VexArchInfo *, const VexAbiInfo *, Int, Int, Bool, Bool, Addr); /* Return the number of bytes of code needed for an event check */ diff --git a/VEX/priv/host_x86_defs.c b/VEX/priv/host_x86_defs.c index 956e323..ac2225c 100644 --- a/VEX/priv/host_x86_defs.c +++ b/VEX/priv/host_x86_defs.c @@ -922,6 +922,13 @@ X86Instr* X86Instr_ProfInc ( void ) { i->tag = Xin_ProfInc; return i; } +X86Instr* X86Instr_IfThenElse(HInstrIfThenElse* hite) +{ + X86Instr* i = LibVEX_Alloc_inline(sizeof(X86Instr)); + i->tag = Xin_IfThenElse; + i->Xin.IfThenElse.hite = hite; + return i; +} void ppX86Instr ( const X86Instr* i, Bool mode64 ) { vassert(mode64 == False); @@ -1212,11 +1219,20 @@ void ppX86Instr ( const X86Instr* i, Bool mode64 ) { vex_printf("(profInc) addl $1,NotKnownYet; " "adcl $0,NotKnownYet+4"); return; + case Xin_IfThenElse: + vex_printf("if (!%s) then {...", + showX86CondCode(i->Xin.IfThenElse.hite->ccOOL)); + return; default: vpanic("ppX86Instr"); } } +void ppX86CondCode(X86CondCode condCode) +{ + vex_printf("%s", showX86CondCode(condCode)); +} + /* --------- Helpers for register allocation. --------- */ void getRegUsage_X86Instr (HRegUsage* u, const X86Instr* i, Bool mode64) @@ -1697,6 +1713,13 @@ Bool isMove_X86Instr ( const X86Instr* i, HReg* src, HReg* dst ) return False; } +extern HInstrIfThenElse* isIfThenElse_X86Instr(X86Instr* i) +{ + if (UNLIKELY(i->tag == Xin_IfThenElse)) { + return i->Xin.IfThenElse.hite; + } + return NULL; +} /* Generate x86 spill/reload instructions under the direction of the register allocator. Note it's critical these don't write the diff --git a/VEX/priv/host_x86_defs.h b/VEX/priv/host_x86_defs.h index 0a3ed75..d6deb96 100644 --- a/VEX/priv/host_x86_defs.h +++ b/VEX/priv/host_x86_defs.h @@ -388,7 +388,8 @@ typedef Xin_SseCMov, /* SSE conditional move */ Xin_SseShuf, /* SSE2 shuffle (pshufd) */ Xin_EvCheck, /* Event check */ - Xin_ProfInc /* 64-bit profile counter increment */ + Xin_ProfInc, /* 64-bit profile counter increment */ + Xin_IfThenElse /* HInstrIfThenElse */ } X86InstrTag; @@ -652,6 +653,9 @@ typedef installed later, post-translation, by patching it in, as it is not known at translation time. */ } ProfInc; + struct { + HInstrIfThenElse* hite; + } IfThenElse; } Xin; } @@ -708,15 +712,18 @@ extern X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst ); extern X86Instr* X86Instr_EvCheck ( X86AMode* amCounter, X86AMode* amFailAddr ); extern X86Instr* X86Instr_ProfInc ( void ); +extern X86Instr* X86Instr_IfThenElse(HInstrIfThenElse*); extern void ppX86Instr ( const X86Instr*, Bool ); +extern void ppX86CondCode(X86CondCode); /* Some functions that insulate the register allocator from details of the underlying instruction set. */ extern void getRegUsage_X86Instr ( HRegUsage*, const X86Instr*, Bool ); extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool ); extern Bool isMove_X86Instr ( const X86Instr*, HReg*, HReg* ); +extern HInstrIfThenElse* isIfThenElse_X86Instr(X86Instr*); extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, const X86Instr* i, Bool mode64, @@ -735,7 +742,7 @@ extern X86Instr* directReload_X86 ( X86Instr* i, HReg vreg, Short spill_off ); extern const RRegUniverse* getRRegUniverse_X86 ( void ); -extern HInstrArray* iselSB_X86 ( const IRSB*, +extern HInstrSB* iselSB_X86 ( const IRSB*, VexArch, const VexArchInfo*, const VexAbiInfo*, |