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From: <sv...@va...> - 2017-04-25 14:41:06
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Author: petarj
Date: Tue Apr 25 15:40:54 2017
New Revision: 3354
Log:
mips: limit cvt.s.l instruction translation to fp_mode64
The documentation says:
"For CVT.S.L, the result of this instruction is UNPREDICTABLE if the
processor is executing in the FR=0 32-bit FPU register model; it is
predictable if executing on a 64-bit FPU in the FR=1 mode, but not with
FR=0, and not on a 32-bit FPU."
Hence the fix.
Modified:
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Tue Apr 25 15:40:54 2017
@@ -13090,12 +13090,16 @@
case 0x15: /* L */
DIP("cvt.s.l %u, %u", fd, fs);
- calculateFCSR(fs, 0, CVTSL, False, 1);
- t0 = newTemp(Ity_I64);
- assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, CVTSL, False, 1);
+ t0 = newTemp(Ity_I64);
+ assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
- putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
- get_IR_roundingmode(), mkexpr(t0))));
+ putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
+ get_IR_roundingmode(), mkexpr(t0))));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
default:
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