Author: sewardj
Date: Tue Oct 18 06:22:51 2016
New Revision: 16066
Log:
Merge from trunk:
16040 mips32: add the test cases for luxc1/suxc1 instructions
Added:
branches/VALGRIND_3_12_BRANCH/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE
- copied unchanged from r16040, trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE
branches/VALGRIND_3_12_BRANCH/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE
- copied unchanged from r16040, trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/none/tests/mips32/Makefile.am
branches/VALGRIND_3_12_BRANCH/none/tests/mips32/vfp.c
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/mips32/Makefile.am
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/mips32/Makefile.am (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/mips32/Makefile.am Tue Oct 18 06:22:51 2016
@@ -6,10 +6,13 @@
EXTRA_DIST = \
block_size.stdout.exp block_size.stderr.exp block_size.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest \
+ bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
+ bug320057-mips32.vgtest \
change_fp_mode.stdout.exp change_fp_mode.stdout.exp-fpu32 \
- change_fp_mode.stderr.exp change_fp_mode.vgtest \
+ change_fp_mode.stderr.exp change_fp_mode.vgtest \
FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
LoadStore.vgtest \
LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
@@ -18,27 +21,25 @@
MIPS32int.stdout.exp-mips32-BE MIPS32int.stdout.exp-mips32r2-BE \
MIPS32int.stdout.exp-mips32-LE MIPS32int.stdout.exp-mips32r2-LE \
MIPS32int.stderr.exp MIPS32int.vgtest \
+ mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
+ mips32_dsp.stderr.exp mips32_dsp.vgtest \
+ mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
+ mips32_dspr2.vgtest \
MoveIns.stdout.exp MoveIns.stdout.exp-BE \
MoveIns.stdout.exp-mips32r2-BE MoveIns.stdout.exp-mips32r2-LE \
MoveIns.stderr.exp MoveIns.vgtest \
+ round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
+ round_fpu64.stderr.exp round_fpu64.vgtest \
round.stdout.exp round.stderr.exp round.vgtest \
- vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
- vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
- vfp.vgtest \
SignalException.stderr.exp SignalException.vgtest \
- bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
- bug320057-mips32.vgtest \
- mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
- mips32_dsp.stderr.exp mips32_dsp.vgtest \
- mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
- mips32_dspr2.vgtest \
- unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
- unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
- round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
- round_fpu64.stderr.exp round_fpu64.vgtest \
- fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest
+ unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
+ unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
+ vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
+ vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
+ vfp.stdout.exp-mips32r2-fpu_64-BE vfp.stdout.exp-mips32r2-fpu_64-LE \
+ vfp.vgtest
check_PROGRAMS = \
allexec \
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/mips32/vfp.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/mips32/vfp.c (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/mips32/vfp.c Tue Oct 18 06:22:51 2016
@@ -1,5 +1,6 @@
#if defined(__mips_hard_float)
-
+#include <setjmp.h>
+#include <signal.h>
#include <stdint.h>
#include <stdio.h>
@@ -15,6 +16,18 @@
0x3FBF9ADD, 0x3746F65F
};
+long long meml[] = {
+ 0x236457894095A266, 0x7777777766666666,
+ 0xBFF00000aaaaccde, 0x0004563217800000,
+ 0x3FF0556644770000, 0x0002255889900000,
+ 0x25254123698a2e2b, 0x21a2b3d6f62d2d2a,
+ 0xFFaabb22ccFFFFFF, 0x542698eeFFFFFFFF,
+ 0x41D2658041D26580, 0xB487E5C9B487E5C9,
+ 0x420774411aa26580, 0xaabbccddB750E388,
+ 0xffffeeee3E45798E, 0xccccccccE2308C3A,
+ 0x123abb983FBF9ADD, 0x002255443746F65F
+};
+
float fs_f[] = {
0, 456.2489562, 3, -1,
1384.6, -7.2945676, 1000000000, -5786.47,
@@ -118,6 +131,22 @@
instruction, (uint32_t)out, (uint32_t)(out >> 32)); \
}
+// luxc1 $f0, $a3($v0)
+#define TESTINSN6LOADlu(instruction, indexVal, fd, index, base) \
+{ \
+ uint64_t out; \
+ __asm__ volatile( \
+ "move $" #base ", %0\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "sdc1 $"#fd ", 0(%1)" \
+ : : "r" (meml), "r" (&out) \
+ : #base, #index, "$"#fd, "memory" \
+ ); \
+ printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \
+ instruction, (uint32_t)out, (uint32_t)(out >> 32)); \
+}
+
// sdc1 $f0, 0($t0)
#define TESTINST1(offset) \
{ \
@@ -158,6 +187,28 @@
out, out1); \
}
+// SUXC1 $f0, $t2($t0)
+#define TESTINST1b(offset, unligned_offset) \
+{ \
+ unsigned int out; \
+ unsigned int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "move $t1, %3\n\t" \
+ "li $t2, "#unligned_offset"\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "suxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ "addi $t0, $t0, 4 \n\t" \
+ "lw %1, "#offset"($t0)\n\t" \
+ : "=r" (out), "=r" (out1) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t2", "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("suxc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \
+ out, out1); \
+}
+
// swc1 $f0, 0($t0)
#define TESTINST2(offset) \
{ \
@@ -195,6 +246,19 @@
out); \
}
+#define TEST_FPU64 \
+ __asm__ __volatile__( \
+ "cvt.l.s $f0, $f0" "\n\t" \
+ : \
+ : \
+ : "$f0" \
+ );
+
+static void handler(int sig)
+{
+ exit(0);
+}
+
void ppMem(double *m, int len)
{
int i;
@@ -405,6 +469,66 @@
ppMemF(mem1f, 16);
#endif
+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64 || __mips_fpr==xx)
+ signal(SIGILL, handler);
+ /* Test fpu64 mode. */
+ TEST_FPU64;
+
+ printf("luxc1\n");
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+
+ printf("SUXC1\n");
+ TESTINST1b(0, 0);
+ TESTINST1b(0, 1);
+ TESTINST1b(8, 8);
+ TESTINST1b(8, 9);
+ TESTINST1b(16, 16);
+ TESTINST1b(16, 17);
+ TESTINST1b(24, 24);
+ TESTINST1b(24, 25);
+ TESTINST1b(32, 32);
+ TESTINST1b(32, 35);
+ TESTINST1b(40, 40);
+ TESTINST1b(40, 42);
+ TESTINST1b(48, 48);
+ TESTINST1b(48, 50);
+ TESTINST1b(56, 56);
+ TESTINST1b(56, 60);
+ TESTINST1b(64, 64);
+ TESTINST1b(64, 67);
+ ppMem(mem1, 16);
+#endif
return 0;
}
#else
|