Author: petarj
Date: Wed Aug 10 15:33:21 2016
New Revision: 3243
Log:
mips32: extend the current fp-mode code to support fpxx features
Part of the changes to support FPXX mode for MIPS32.
Patch by Aleksandar Rikalo <Ale...@im...>
Related issue BZ #366079.
Modified:
trunk/priv/guest_mips_helpers.c
trunk/priv/guest_mips_toIR.c
trunk/priv/host_mips_isel.c
trunk/pub/libvex.h
trunk/pub/libvex_guest_mips32.h
trunk/pub/libvex_guest_mips64.h
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Wed Aug 10 15:33:21 2016
@@ -165,6 +165,8 @@
vex_state->guest_COND = 0;
+ vex_state->guest_CP0_status = 0;
+
/* MIPS32 DSP ASE(r2) specific registers */
vex_state->guest_DSPControl = 0; /* DSPControl register */
vex_state->guest_ac0 = 0; /* Accumulator 0 */
@@ -272,6 +274,8 @@
vex_state->guest_NRADDR = 0;
vex_state->guest_COND = 0;
+
+ vex_state->guest_CP0_status = MIPS_CP0_STATUS_FR;
}
/*-----------------------------------------------------------*/
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Wed Aug 10 15:33:21 2016
@@ -17300,10 +17300,7 @@
vassert(guest_arch == VexArchMIPS32 || guest_arch == VexArchMIPS64);
mode64 = guest_arch != VexArchMIPS32;
-#if (__mips_fpr==64)
- fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(archinfo->hwcaps)
- || guest_arch == VexArchMIPS64);
-#endif
+ fp_mode64 = abiinfo->guest_mips_fp_mode64;
guest_code = guest_code_IN;
irsb = irsb_IN;
Modified: trunk/priv/host_mips_isel.c
==============================================================================
--- trunk/priv/host_mips_isel.c (original)
+++ trunk/priv/host_mips_isel.c Wed Aug 10 15:33:21 2016
@@ -4183,10 +4183,7 @@
|| archinfo_host->endness == VexEndnessBE);
mode64 = arch_host != VexArchMIPS32;
-#if (__mips_fpr==64)
- fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(hwcaps_host)
- || arch_host == VexArchMIPS64);
-#endif
+ fp_mode64 = VEX_MIPS_HOST_FP_MODE(hwcaps_host);
/* Make up an initial environment to use. */
env = LibVEX_Alloc_inline(sizeof(ISelEnv));
Modified: trunk/pub/libvex.h
==============================================================================
--- trunk/pub/libvex.h (original)
+++ trunk/pub/libvex.h Wed Aug 10 15:33:21 2016
@@ -227,8 +227,7 @@
/*
* Instead of Company Options values, bits 31:24 will be packed with
- * additional information, such as isa level and presence of FPU unit
- * with 32 64-bit registers.
+ * additional information, such as isa level and FP mode.
*/
#define VEX_MIPS_CPU_ISA_M32R1 0x01000000
#define VEX_MIPS_CPU_ISA_M32R2 0x02000000
@@ -236,8 +235,8 @@
#define VEX_MIPS_CPU_ISA_M64R2 0x08000000
#define VEX_MIPS_CPU_ISA_M32R6 0x10000000
#define VEX_MIPS_CPU_ISA_M64R6 0x20000000
-/* CPU has FPU and 32 dbl. prec. FP registers */
-#define VEX_MIPS_CPU_32FPR 0x40000000
+/* FP mode is FR = 1 (32 dbl. prec. FP registers) */
+#define VEX_MIPS_HOST_FR 0x40000000
/* Get MIPS Extended Information */
#define VEX_MIPS_EX_INFO(x) ((x) & 0xFF000000)
/* Get MIPS Company ID from HWCAPS */
@@ -246,10 +245,10 @@
#define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00)
/* Get MIPS Revision from HWCAPS */
#define VEX_MIPS_REV(x) ((x) & 0x000000FF)
-/* Check if the processor has 32 64-bit FP registers */
-#define VEX_MIPS_HAS_32_64BIT_FPRS(x) (VEX_MIPS_EX_INFO(x) | VEX_MIPS_CPU_32FPR)
+/* Get host FP mode */
+#define VEX_MIPS_HOST_FP_MODE(x) (!!(VEX_MIPS_EX_INFO(x) & VEX_MIPS_HOST_FR))
/* Check if the processor supports MIPS32R2. */
-#define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) | \
+#define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) & \
VEX_MIPS_CPU_ISA_M32R2)
/* Check if the processor supports DSP ASE Rev 2. */
#define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
@@ -406,6 +405,8 @@
function descriptor on the host, or to the function code
itself? True => descriptor, False => code. */
Bool host_ppc_calls_use_fndescrs;
+
+ Bool guest_mips_fp_mode64;
}
VexAbiInfo;
Modified: trunk/pub/libvex_guest_mips32.h
==============================================================================
--- trunk/pub/libvex_guest_mips32.h (original)
+++ trunk/pub/libvex_guest_mips32.h Wed Aug 10 15:33:21 2016
@@ -147,7 +147,9 @@
/* 472 */ ULong guest_ac2;
/* 480 */ ULong guest_ac3;
- UInt padding;
+ /* 488 */ UInt guest_CP0_status;
+
+ /* 492 */ UInt padding;
} VexGuestMIPS32State;
/*---------------------------------------------------------------*/
/*--- Utility functions for MIPS32 guest stuff. ---*/
@@ -160,6 +162,8 @@
extern
void LibVEX_GuestMIPS32_initialise ( /*OUT*/VexGuestMIPS32State* vex_state );
+/* FR bit of CP0_STATUS_FR register */
+#define MIPS_CP0_STATUS_FR (1ul << 26)
#endif /* ndef __LIBVEX_PUB_GUEST_MIPS32_H */
Modified: trunk/pub/libvex_guest_mips64.h
==============================================================================
--- trunk/pub/libvex_guest_mips64.h (original)
+++ trunk/pub/libvex_guest_mips64.h Wed Aug 10 15:33:21 2016
@@ -123,6 +123,8 @@
/* 548 */ UInt guest_FENR;
/* 552 */ UInt guest_FCSR;
+ /* 556 */ UInt guest_CP0_status;
+
/* TLS pointer for the thread. It's read-only in user space. On Linux it
is set in user space by various thread-related syscalls.
User Local Register.
@@ -159,6 +161,9 @@
extern
void LibVEX_GuestMIPS64_initialise ( /*OUT*/VexGuestMIPS64State* vex_state );
+/* FR bit of CP0_STATUS_FR register */
+#define MIPS_CP0_STATUS_FR (1ul << 26)
+
#endif /* ndef __LIBVEX_PUB_GUEST_MIPS64_H */
/*---------------------------------------------------------------*/
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