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From: <sv...@va...> - 2016-06-13 17:27:11
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Author: carll
Date: Mon Jun 13 18:27:03 2016
New Revision: 3221
Log:
Fix mtfsfi usage of W bit. (isa2.05,ppc64)
Fix mtfsfi usage of W bit.
The Wbit field was added in ISA 2.05, allowing updates to the 'other'
half of the 64-bit FPSCR field.
Logic and Support for that bit is in place, but a 'reserved field
must contain zeros' check was not updated, preventing the desired
path from being taken.
Bugzilla 362894
Signed-off-by: Will Schmidt <wil...@vn...>
Patch reviewed and verified by: Carl Love <ce...@ib...>
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Mon Jun 13 18:27:03 2016
@@ -10529,24 +10529,16 @@
case 0x086: { // mtfsfi (Move to FPSCR Field Immediate, PPC32 p481)
UInt crfD = IFIELD( theInstr, 23, 3 );
- UChar b16to22 = toUChar( IFIELD( theInstr, 16, 7 ) );
+ UChar b17to22 = toUChar( IFIELD( theInstr, 17, 6 ) );
UChar IMM = toUChar( IFIELD( theInstr, 12, 4 ) );
UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) );
- UChar Wbit;
+ UChar Wbit = toUChar( IFIELD( theInstr, 16, 1 ) );
- if (b16to22 != 0 || b11 != 0) {
+ if (b17to22 != 0 || b11 != 0 || (Wbit && !GX_level)) {
vex_printf("dis_fp_scr(ppc)(instr,mtfsfi)\n");
return False;
- }
- DIP("mtfsfi%s crf%u,%d\n", flag_rC ? ".":"", crfD, IMM);
- if (GX_level) {
- /* This implies that Decimal Floating Point is supported, and the
- * FPSCR must be managed as a 64-bit register.
- */
- Wbit = toUChar( IFIELD(theInstr, 16, 1) );
- } else {
- Wbit = 0;
}
+ DIP("mtfsfi%s crf%u,%d%s\n", flag_rC ? ".":"", crfD, IMM, Wbit ? ",1":"");
crfD = crfD + (8 * (1 - Wbit) );
putGST_field( PPC_GST_FPSCR, mkU32( IMM ), crfD );
break;
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