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From: James D. <J.H...@ba...> - 2015-04-11 08:10:33
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On Fri, 10 Apr 2015, Josef Weidendorfer <Jos...@gm...> wrote On Fri, 10 Apr 2015, Josef Weidendorfer <Jos...@gm...> wrote Subject: Re: [Valgrind-developers] Characteristics of VG simulated CPU My student Stavros Kaparelos (ska...@gm...) has a modification for Cachegrind that tracks L1/L2/L3 separately, and that also tracks TLB as well. James Davenport Am 10.04.2015 um 10:44 schrieb Alex: > Can someone provide a quick explanation what are the characteristics > of VG simulated CPU (cache, cores, core speed, threads)? Cachegrind/Callgrind simulate one 2-level cache hierarchy with separate L1 data and L1 instuction caches, and unified L2. L1 and L2 are inclusive (not strict inclusive) with write-allocate and LRU replacement. Cache parameters (associativity/sizes) are taken per default from the CPU you run VG on. For newer Intel CPUs with L3, the real L3 parameters are used for the L2 in the cache model. As events, you get number of instructions executed (= fetched from L1), data read and written from/to L1, L1D/L1I and L2 misses. James Davenport National Teaching Fellow 2014 Hebron & Medlock Professor of Information Technology, University of Bath OpenMath Content Dictionary Editor Director of Studies EPSRC Doctoral Taught Course Centre for HPC Chair, IMU Committee on Electronic Information and Communication Vice-President and Academy Trustee, British Computer Society SW Coordinator, Computing at School Network of Excellence |