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From: <sv...@va...> - 2015-01-18 16:39:11
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Author: sewardj
Date: Sun Jan 18 16:39:04 2015
New Revision: 3069
Log:
Move AMD64Instr case NCode into its own struct, since having it
in-line in AMD64Instr increases the size of it from 40 to 48 bytes,
and we allocate a lot of AMD64Instrs.
Modified:
branches/NCODE/priv/host_amd64_defs.c
branches/NCODE/priv/host_amd64_defs.h
branches/NCODE/priv/host_generic_reg_alloc2.c
branches/NCODE/priv/main_main.c
Modified: branches/NCODE/priv/host_amd64_defs.c
==============================================================================
--- branches/NCODE/priv/host_amd64_defs.c (original)
+++ branches/NCODE/priv/host_amd64_defs.c Sun Jan 18 16:39:04 2015
@@ -1034,13 +1034,15 @@
}
AMD64Instr* AMD64Instr_NCode ( NCodeTemplate* tmpl, HReg* regsR,
HReg* regsA, HReg* regsS ) {
+ AMD64InstrNCode* details = LibVEX_Alloc(sizeof(AMD64InstrNCode));
+ details->tmpl = tmpl;
+ details->regsR = regsR;
+ details->regsA = regsA;
+ details->regsS = regsS;
+ details->liveAfter = NULL;
AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
- i->tag = Ain_NCode;
- i->Ain.NCode.tmpl = tmpl;
- i->Ain.NCode.regsR = regsR;
- i->Ain.NCode.regsA = regsA;
- i->Ain.NCode.regsS = regsS;
- i->Ain.NCode.liveAfter = NULL;
+ i->tag = Ain_NCode;
+ i->Ain.NCode.details = details;
return i;
}
AMD64Instr* AMD64Instr_NC_Jmp32 ( AMD64CondCode cc ) {
@@ -1380,20 +1382,21 @@
return;
case Ain_NCode: {
UInt j;
- NCodeTemplate* tmpl = i->Ain.NCode.tmpl;
+ AMD64InstrNCode* details = i->Ain.NCode.details;
+ NCodeTemplate* tmpl = details->tmpl;
vex_printf("NCode-AMD64:%s [", tmpl->name);
for (j = 0; j < tmpl->nres; j++) {
- ppHRegAMD64(i->Ain.NCode.regsR[j]);
+ ppHRegAMD64(details->regsR[j]);
if (j != tmpl->nres-1) vex_printf(" ");
}
vex_printf("] <= [");
for (j = 0; j < tmpl->narg; j++) {
- ppHRegAMD64(i->Ain.NCode.regsA[j]);
+ ppHRegAMD64(details->regsA[j]);
if (j != tmpl->narg-1) vex_printf(" ");
}
vex_printf("] scratch [");
for (j = 0; j < tmpl->nscr; j++) {
- ppHRegAMD64(i->Ain.NCode.regsS[j]);
+ ppHRegAMD64(details->regsS[j]);
if (j != tmpl->nscr-1) vex_printf(" ");
}
vex_printf("]");
@@ -1726,13 +1729,14 @@
addHRegUse(u, HRmWrite, hregAMD64_R11());
return;
case Ain_NCode: {
- UInt j;
- NCodeTemplate* tmpl = i->Ain.NCode.tmpl;
+ AMD64InstrNCode* details = i->Ain.NCode.details;
+ NCodeTemplate* tmpl = details->tmpl;
// It writes the result and scratch registers.
+ UInt j;
for (j = 0; j < tmpl->nres; j++)
- addHRegUse(u, HRmWrite, i->Ain.NCode.regsR[j]);
+ addHRegUse(u, HRmWrite, details->regsR[j]);
for (j = 0; j < tmpl->nscr; j++)
- addHRegUse(u, HRmWrite, i->Ain.NCode.regsS[j]);
+ addHRegUse(u, HRmWrite, details->regsS[j]);
// It both reads and writes the arg regs. We have to say
// they are written in order to force them to be allocated
// different registers from the arg and scratch registers,
@@ -1740,7 +1744,7 @@
// doesn't write its scratch and result registers and later
// on read the argument registers.
for (j = 0; j < tmpl->narg; j++)
- addHRegUse(u, HRmModify, i->Ain.NCode.regsA[j]);
+ addHRegUse(u, HRmModify, details->regsA[j]);
return;
}
default:
@@ -1931,14 +1935,15 @@
/* hardwires r11 -- nothing to modify. */
return;
case Ain_NCode: {
+ AMD64InstrNCode* details = i->Ain.NCode.details;
+ NCodeTemplate* tmpl = details->tmpl;
UInt j;
- NCodeTemplate* tmpl = i->Ain.NCode.tmpl;
for (j = 0; j < tmpl->nres; j++)
- mapReg(m, &i->Ain.NCode.regsR[j]);
+ mapReg(m, &details->regsR[j]);
for (j = 0; j < tmpl->nscr; j++)
- mapReg(m, &i->Ain.NCode.regsS[j]);
+ mapReg(m, &details->regsS[j]);
for (j = 0; j < tmpl->narg; j++)
- mapReg(m, &i->Ain.NCode.regsA[j]);
+ mapReg(m, &details->regsA[j]);
return;
}
default:
@@ -3792,20 +3797,22 @@
Bool emit_AMD64NCode ( /*MOD*/AssemblyBuffer* ab_hot,
/*MOD*/AssemblyBuffer* ab_cold,
/*MOD*/RelocationBuffer* rb,
- const AMD64Instr* hi,
+ const AMD64Instr* hi,
Bool mode64, VexEndness endness_host,
Bool verbose )
{
vassert(mode64 == True);
vassert(endness_host == VexEndnessLE);
vassert(hi->tag == Ain_NCode);
- const NCodeTemplate* tmpl = hi->Ain.NCode.tmpl;
- const HRegSet* hregsLiveAfter = hi->Ain.NCode.liveAfter;
+
+ const AMD64InstrNCode* hi_details = hi->Ain.NCode.details;
+ const NCodeTemplate* tmpl = hi_details->tmpl;
+ const HRegSet* hregsLiveAfter = hi_details->liveAfter;
NRegMap nregMap;
- nregMap.regsR = hi->Ain.NCode.regsR;
- nregMap.regsA = hi->Ain.NCode.regsA;
- nregMap.regsS = hi->Ain.NCode.regsS;
+ nregMap.regsR = hi_details->regsR;
+ nregMap.regsA = hi_details->regsA;
+ nregMap.regsS = hi_details->regsS;
nregMap.nRegsR = tmpl->nres;
nregMap.nRegsA = tmpl->narg;
nregMap.nRegsS = tmpl->nscr;
Modified: branches/NCODE/priv/host_amd64_defs.h
==============================================================================
--- branches/NCODE/priv/host_amd64_defs.h (original)
+++ branches/NCODE/priv/host_amd64_defs.h Sun Jan 18 16:39:04 2015
@@ -467,6 +467,21 @@
}
AMD64InstrTag;
+
+/* --------- */
+typedef
+ struct {
+ NCodeTemplate* tmpl;
+ HReg* regsR; /* Result regs, INVALID_HREG terminated */
+ HReg* regsA; /* Arg regs, ditto */
+ HReg* regsS; /* Scratch regs, ditto */
+ HRegSet* liveAfter; /* initially NULL, filled in by RA */
+ }
+ AMD64InstrNCode;
+
+
+/* --------- */
+
/* Destinations are on the RIGHT (second operand) */
typedef
@@ -754,11 +769,8 @@
as it is not known at translation time. */
} ProfInc;
struct {
- NCodeTemplate* tmpl;
- HReg* regsR; /* Result regs, INVALID_HREG terminated */
- HReg* regsA; /* Arg regs, ditto */
- HReg* regsS; /* Scratch regs, ditto */
- HRegSet* liveAfter; /* initially NULL, filled in by RA */
+ /* Out of line so as to keep sizeof(AMD64Instr) at 40. */
+ AMD64InstrNCode* details;
} NCode;
/* --- for NCode only --- */
@@ -856,10 +868,10 @@
const AMD64Instr*, Bool, VexEndness,
const VexDispatcherAddresses* );
-extern Bool emit_AMD64NCode ( /*MOD*/AssemblyBuffer* ab_hot,
- /*MOD*/AssemblyBuffer* ab_cold,
+extern Bool emit_AMD64NCode ( /*MOD*/AssemblyBuffer* ab_hot,
+ /*MOD*/AssemblyBuffer* ab_cold,
/*MOD*/RelocationBuffer* rb,
- const AMD64Instr* i,
+ const AMD64Instr* hi,
Bool mode64, VexEndness endness_host,
Bool verbose );
Modified: branches/NCODE/priv/host_generic_reg_alloc2.c
==============================================================================
--- branches/NCODE/priv/host_generic_reg_alloc2.c (original)
+++ branches/NCODE/priv/host_generic_reg_alloc2.c Sun Jan 18 16:39:04 2015
@@ -1543,8 +1543,9 @@
set of registers that are live after it. */
{ AMD64Instr* ai = instrs_in->arr[ii];
if (ai->tag == Ain_NCode) {
+ AMD64InstrNCode* details = ai->Ain.NCode.details;
//vex_printf("RA: after NCode: ");
- vassert(ai->Ain.NCode.liveAfter == NULL);
+ vassert(details->liveAfter == NULL);
HRegSet* live_after_NCode = HRegSet__new();
for (k = 0; k < n_rregs; k++) {
if (rreg_state[k].disp == Free)
@@ -1554,7 +1555,7 @@
//vex_printf(" ");
}
//vex_printf("\n");
- ai->Ain.NCode.liveAfter = live_after_NCode;
+ details->liveAfter = live_after_NCode;
}
}
Modified: branches/NCODE/priv/main_main.c
==============================================================================
--- branches/NCODE/priv/main_main.c (original)
+++ branches/NCODE/priv/main_main.c Sun Jan 18 16:39:04 2015
@@ -391,6 +391,7 @@
emit = (__typeof__(emit)) emit_AMD64Instr;
host_word_type = Ity_I64;
vassert(vta->archinfo_host.endness == VexEndnessLE);
+ vassert(sizeof(AMD64Instr) <= 40); /* avoid space regressions */
break;
#if 0
case VexArchPPC32:
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