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From: <sv...@va...> - 2014-11-19 16:07:39
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Author: sewardj
Date: Wed Nov 19 16:07:28 2014
New Revision: 2995
Log:
Implement VFPv4 VFNMA, VFNMS d_d and s_s variants (not that
there are any other variants). Fixes #340807.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Wed Nov 19 16:07:28 2014
@@ -13529,6 +13529,28 @@
condT);
DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
goto decode_success_vfp;
+ case BITS4(1,0,1,0): /* VNFMS: -(d - n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putDReg(dD, triop(Iop_AddF64, rm,
+ unop(Iop_NegF64, getDReg(dD)),
+ triop(Iop_MulF64, rm,
+ getDReg(dN),
+ getDReg(dM))),
+ condT);
+ DIP("vfnmsd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+ goto decode_success_vfp;
+ case BITS4(1,0,1,1): /* VNFMA: -(d + n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putDReg(dD, triop(Iop_AddF64, rm,
+ unop(Iop_NegF64, getDReg(dD)),
+ triop(Iop_MulF64, rm,
+ unop(Iop_NegF64, getDReg(dN)),
+ getDReg(dM))),
+ condT);
+ DIP("vfnmad%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+ goto decode_success_vfp;
case BITS4(1,1,0,0): /* VFMA: d + n * m (fused) */
/* XXXROUNDINGFIXME look up ARM reference for fused
multiply-add rounding */
@@ -14014,6 +14036,28 @@
condT);
DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
goto decode_success_vfp;
+ case BITS4(1,0,1,0): /* VNFMS: -(d - n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putFReg(fD, triop(Iop_AddF32, rm,
+ unop(Iop_NegF32, getFReg(fD)),
+ triop(Iop_MulF32, rm,
+ getFReg(fN),
+ getFReg(fM))),
+ condT);
+ DIP("vfnmss%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+ goto decode_success_vfp;
+ case BITS4(1,0,1,1): /* VNFMA: -(d + n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putFReg(fD, triop(Iop_AddF32, rm,
+ unop(Iop_NegF32, getFReg(fD)),
+ triop(Iop_MulF32, rm,
+ unop(Iop_NegF32, getFReg(fN)),
+ getFReg(fM))),
+ condT);
+ DIP("vfnmas%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+ goto decode_success_vfp;
case BITS4(1,1,0,0): /* VFMA: d + n * m (fused) */
/* XXXROUNDINGFIXME look up ARM reference for fused
multiply-add rounding */
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