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From: <sv...@va...> - 2014-11-15 22:15:59
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Author: sewardj
Date: Sat Nov 15 22:15:47 2014
New Revision: 14728
Log:
Add test cases for all remaining AArch64 ARMv8 SIMD and FP instructions.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
trunk/none/tests/arm64/fp_and_simd.stdout.exp
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Sat Nov 15 22:15:47 2014
@@ -23,7 +23,7 @@
#define ITERS 1
typedef
- enum { TySF=1234, TyDF, TyB, TyH, TyS, TyD, TyNONE }
+ enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
LaneTy;
union _V128 {
@@ -2437,74 +2437,243 @@
// ======================== CONV ========================
-// fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
+GEN_TWOVEC_TEST(fcvt_s_h, "fcvt s7, h16", 7, 16)
+GEN_TWOVEC_TEST(fcvt_d_h, "fcvt d7, h16", 7, 16)
+GEN_TWOVEC_TEST(fcvt_h_s, "fcvt h7, s16", 7, 16)
+GEN_TWOVEC_TEST(fcvt_d_s, "fcvt d7, s16", 7, 16)
+GEN_TWOVEC_TEST(fcvt_h_d, "fcvt h7, d16", 7, 16)
+GEN_TWOVEC_TEST(fcvt_s_d, "fcvt s7, d16", 7, 16)
+
+GEN_TWOVEC_TEST(fcvtl_4s_4h, "fcvtl v11.4s, v29.4h", 11, 29)
+GEN_TWOVEC_TEST(fcvtl_4s_8h, "fcvtl2 v11.4s, v29.8h", 11, 29)
+GEN_TWOVEC_TEST(fcvtl_2d_2s, "fcvtl v11.2d, v29.2s", 11, 29)
+GEN_TWOVEC_TEST(fcvtl_2d_4s, "fcvtl2 v11.2d, v29.4s", 11, 29)
-// fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
-
-// fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
-// INCOMPLETE
+GEN_TWOVEC_TEST(fcvtn_4h_4s, "fcvtn v22.4h, v23.4s", 22, 23)
+GEN_TWOVEC_TEST(fcvtn_8h_4s, "fcvtn2 v22.8h, v23.4s", 22, 23)
GEN_TWOVEC_TEST(fcvtn_2s_2d, "fcvtn v22.2s, v23.2d", 22, 23)
GEN_TWOVEC_TEST(fcvtn_4s_2d, "fcvtn2 v22.4s, v23.2d", 22, 23)
-// fcvtas d,s (fcvt to signed int, nearest, ties away)
-// fcvtau d,s (fcvt to unsigned int, nearest, ties away)
-// fcvtas 2d,4s,2s
-// fcvtau 2d,4s,2s
-// fcvtas w_s,x_s,w_d,x_d
-// fcvtau w_s,x_s,w_d,x_d
-
-// fcvtms d,s (fcvt to signed int, minus inf)
-// fcvtmu d,s (fcvt to unsigned int, minus inf)
-// fcvtms 2d,4s,2s
-// fcvtmu 2d,4s,2s
-// fcvtms w_s,x_s,w_d,x_d
-// fcvtmu w_s,x_s,w_d,x_d
-
-// fcvtns d,s (fcvt to signed int, nearest)
-// fcvtnu d,s (fcvt to unsigned int, nearest)
-// fcvtns 2d,4s,2s
-// fcvtnu 2d,4s,2s
-// fcvtns w_s,x_s,w_d,x_d
-// fcvtnu w_s,x_s,w_d,x_d
-
-// fcvtps d,s (fcvt to signed int, plus inf)
-// fcvtpu d,s (fcvt to unsigned int, plus inf)
-// fcvtps 2d,4s,2s
-// fcvtpu 2d,4s,2s
-// fcvtps w_s,x_s,w_d,x_d
-// fcvtpu w_s,x_s,w_d,x_d
-
-// fcvtzs d,s (fcvt to signed integer, to zero)
-// fcvtzu d,s (fcvt to unsigned integer, to zero)
-// fcvtzs 2d,4s,2s
-// fcvtzu 2d,4s,2s
-// fcvtzs w_s,x_s,w_d,x_d
-// fcvtzu w_s,x_s,w_d,x_d
-
-// fcvtzs d,s (fcvt to signed fixedpt, to zero) (w/ #fbits)
-// fcvtzu d,s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
-// fcvtzs 2d,4s,2s
-// fcvtzu 2d,4s,2s
-// fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits)
-// fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
-
-// fcvtxn s_d (fcvt to lower prec narrow, rounding to odd)
-// fcvtxn 2s_2d,4s_2d
-
-// scvtf d,s _#fbits
-// ucvtf d,s _#fbits
-
-// scvtf 2d,4s,2s _#fbits
-// ucvtf 2d,4s,2s _#fbits
-
-// scvtf d,s
-// ucvtf d,s
-
-// scvtf 2d,4s,2s
-// ucvtf 2d,4s,2s
-
-// scvtf s_w, d_w, s_x, d_x, _#fbits
-// ucvtf s_w, d_w, s_x, d_x, _#fbits
+GEN_TWOVEC_TEST(fcvtas_d_d, "fcvtas d10, d21", 10, 21)
+GEN_TWOVEC_TEST(fcvtau_d_d, "fcvtau d21, d10", 21, 10)
+GEN_TWOVEC_TEST(fcvtas_s_s, "fcvtas s10, s21", 10, 21)
+GEN_TWOVEC_TEST(fcvtau_s_s, "fcvtau s21, s10", 21, 10)
+GEN_TWOVEC_TEST(fcvtas_2d_2d, "fcvtas v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtau_2d_2d, "fcvtau v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtas_4s_4s, "fcvtas v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtau_4s_4s, "fcvtau v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtas_2s_2s, "fcvtas v10.2s, v21.2s", 10, 21)
+GEN_TWOVEC_TEST(fcvtau_2s_2s, "fcvtau v10.2s, v21.2s", 10, 21)
+GEN_ONEINT_ONEVEC_TEST(fcvtas_w_s, "fcvtas w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtau_w_s, "fcvtau w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtas_x_s, "fcvtas x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtau_x_s, "fcvtau x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtas_w_d, "fcvtas w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtau_w_d, "fcvtau w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtas_x_d, "fcvtas x21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtau_x_d, "fcvtau x21, d10", 21, 10)
+
+GEN_TWOVEC_TEST(fcvtms_d_d, "fcvtms d10, d21", 10, 21)
+GEN_TWOVEC_TEST(fcvtmu_d_d, "fcvtmu d21, d10", 21, 10)
+GEN_TWOVEC_TEST(fcvtms_s_s, "fcvtms s10, s21", 10, 21)
+GEN_TWOVEC_TEST(fcvtmu_s_s, "fcvtmu s21, s10", 21, 10)
+GEN_TWOVEC_TEST(fcvtms_2d_2d, "fcvtms v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtmu_2d_2d, "fcvtmu v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtms_4s_4s, "fcvtms v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtmu_4s_4s, "fcvtmu v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtms_2s_2s, "fcvtms v10.2s, v21.2s", 10, 21)
+GEN_TWOVEC_TEST(fcvtmu_2s_2s, "fcvtmu v10.2s, v21.2s", 10, 21)
+GEN_ONEINT_ONEVEC_TEST(fcvtms_w_s, "fcvtms w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtmu_w_s, "fcvtmu w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtms_x_s, "fcvtms x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtmu_x_s, "fcvtmu x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtms_w_d, "fcvtms w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtmu_w_d, "fcvtmu w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtms_x_d, "fcvtms x21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtmu_x_d, "fcvtmu x21, d10", 21, 10)
+
+GEN_TWOVEC_TEST(fcvtns_d_d, "fcvtns d10, d21", 10, 21)
+GEN_TWOVEC_TEST(fcvtnu_d_d, "fcvtnu d21, d10", 21, 10)
+GEN_TWOVEC_TEST(fcvtns_s_s, "fcvtns s10, s21", 10, 21)
+GEN_TWOVEC_TEST(fcvtnu_s_s, "fcvtnu s21, s10", 21, 10)
+GEN_TWOVEC_TEST(fcvtns_2d_2d, "fcvtns v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtnu_2d_2d, "fcvtnu v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtns_4s_4s, "fcvtns v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtnu_4s_4s, "fcvtnu v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtns_2s_2s, "fcvtns v10.2s, v21.2s", 10, 21)
+GEN_TWOVEC_TEST(fcvtnu_2s_2s, "fcvtnu v10.2s, v21.2s", 10, 21)
+GEN_ONEINT_ONEVEC_TEST(fcvtns_w_s, "fcvtns w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtnu_w_s, "fcvtnu w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtns_x_s, "fcvtns x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtnu_x_s, "fcvtnu x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtns_w_d, "fcvtns w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtnu_w_d, "fcvtnu w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtns_x_d, "fcvtns x21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtnu_x_d, "fcvtnu x21, d10", 21, 10)
+
+GEN_TWOVEC_TEST(fcvtps_d_d, "fcvtps d10, d21", 10, 21)
+GEN_TWOVEC_TEST(fcvtpu_d_d, "fcvtpu d21, d10", 21, 10)
+GEN_TWOVEC_TEST(fcvtps_s_s, "fcvtps s10, s21", 10, 21)
+GEN_TWOVEC_TEST(fcvtpu_s_s, "fcvtpu s21, s10", 21, 10)
+GEN_TWOVEC_TEST(fcvtps_2d_2d, "fcvtps v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtpu_2d_2d, "fcvtpu v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtps_4s_4s, "fcvtps v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtpu_4s_4s, "fcvtpu v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtps_2s_2s, "fcvtps v10.2s, v21.2s", 10, 21)
+GEN_TWOVEC_TEST(fcvtpu_2s_2s, "fcvtpu v10.2s, v21.2s", 10, 21)
+GEN_ONEINT_ONEVEC_TEST(fcvtps_w_s, "fcvtps w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtpu_w_s, "fcvtpu w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtps_x_s, "fcvtps x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtpu_x_s, "fcvtpu x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtps_w_d, "fcvtps w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtpu_w_d, "fcvtpu w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtps_x_d, "fcvtps x21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtpu_x_d, "fcvtpu x21, d10", 21, 10)
+
+GEN_TWOVEC_TEST(fcvtzs_d_d, "fcvtzs d10, d21", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_d_d, "fcvtzu d21, d10", 21, 10)
+GEN_TWOVEC_TEST(fcvtzs_s_s, "fcvtzs s10, s21", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_s_s, "fcvtzu s21, s10", 21, 10)
+GEN_TWOVEC_TEST(fcvtzs_2d_2d, "fcvtzs v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2d_2d, "fcvtzu v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_4s_4s, "fcvtzs v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_4s_4s, "fcvtzu v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2s_2s, "fcvtzs v10.2s, v21.2s", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2s_2s, "fcvtzu v10.2s, v21.2s", 10, 21)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s, "fcvtzs w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s, "fcvtzu w21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s, "fcvtzs x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s, "fcvtzu x21, s10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d, "fcvtzs w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d, "fcvtzu w21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d, "fcvtzs x21, d10", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d, "fcvtzu x21, d10", 21, 10)
+
+GEN_TWOVEC_TEST(fcvtzs_d_d_fbits1, "fcvtzs d10, d21, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_d_d_fbits32, "fcvtzs d10, d21, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_d_d_fbits64, "fcvtzs d10, d21, #64", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_d_d_fbits1, "fcvtzu d10, d21, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_d_d_fbits32, "fcvtzu d10, d21, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_d_d_fbits64, "fcvtzu d10, d21, #64", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_s_s_fbits1, "fcvtzs s10, s21, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_s_s_fbits16, "fcvtzs s10, s21, #16", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_s_s_fbits32, "fcvtzs s10, s21, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_s_s_fbits1, "fcvtzu s10, s21, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_s_s_fbits16, "fcvtzu s10, s21, #16", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_s_s_fbits32, "fcvtzu s10, s21, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2d_2d_fbits1, "fcvtzs v10.2d, v21.2d, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2d_2d_fbits32, "fcvtzs v10.2d, v21.2d, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2d_2d_fbits64, "fcvtzs v10.2d, v21.2d, #64", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2d_2d_fbits1, "fcvtzu v10.2d, v21.2d, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2d_2d_fbits32, "fcvtzu v10.2d, v21.2d, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2d_2d_fbits64, "fcvtzu v10.2d, v21.2d, #64", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_4s_4s_fbits1, "fcvtzs v10.4s, v21.4s, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_4s_4s_fbits16, "fcvtzs v10.4s, v21.4s, #16", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_4s_4s_fbits32, "fcvtzs v10.4s, v21.4s, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_4s_4s_fbits1, "fcvtzu v10.4s, v21.4s, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_4s_4s_fbits16, "fcvtzu v10.4s, v21.4s, #16", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_4s_4s_fbits32, "fcvtzu v10.4s, v21.4s, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2s_2s_fbits1, "fcvtzs v10.2s, v21.2s, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2s_2s_fbits16, "fcvtzs v10.2s, v21.2s, #16", 10, 21)
+GEN_TWOVEC_TEST(fcvtzs_2s_2s_fbits32, "fcvtzs v10.2s, v21.2s, #32", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2s_2s_fbits1, "fcvtzu v10.2s, v21.2s, #1", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2s_2s_fbits16, "fcvtzu v10.2s, v21.2s, #16", 10, 21)
+GEN_TWOVEC_TEST(fcvtzu_2s_2s_fbits32, "fcvtzu v10.2s, v21.2s, #32", 10, 21)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s_fbits1, "fcvtzs w21, s10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s_fbits16, "fcvtzs w21, s10, #16", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s_fbits32, "fcvtzs w21, s10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s_fbits1, "fcvtzu w21, s10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s_fbits16, "fcvtzu w21, s10, #16", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s_fbits32, "fcvtzu w21, s10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s_fbits1, "fcvtzs x21, s10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s_fbits32, "fcvtzs x21, s10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s_fbits64, "fcvtzs x21, s10, #64", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s_fbits1, "fcvtzu x21, s10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s_fbits32, "fcvtzu x21, s10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s_fbits64, "fcvtzu x21, s10, #64", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d_fbits1, "fcvtzs w21, d10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d_fbits16, "fcvtzs w21, d10, #16", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d_fbits32, "fcvtzs w21, d10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d_fbits1, "fcvtzu w21, d10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d_fbits16, "fcvtzu w21, d10, #16", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d_fbits32, "fcvtzu w21, d10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d_fbits1, "fcvtzs x21, d10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d_fbits32, "fcvtzs x21, d10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d_fbits64, "fcvtzs x21, d10, #64", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d_fbits1, "fcvtzu x21, d10, #1", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d_fbits32, "fcvtzu x21, d10, #32", 21, 10)
+GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d_fbits64, "fcvtzu x21, d10, #64", 21, 10)
+
+GEN_TWOVEC_TEST(fcvtxn_s_d, "fcvtxn s10, d21", 10, 21)
+GEN_TWOVEC_TEST(fcvtxn_2s_2d, "fcvtxn v10.2s, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(fcvtxn_4s_2d, "fcvtxn2 v10.4s, v21.2d", 10, 21)
+
+GEN_TWOVEC_TEST(scvtf_d_d_fbits1, "scvtf d10, d21 , #1", 10, 21)
+GEN_TWOVEC_TEST(scvtf_d_d_fbits32, "scvtf d10, d21 , #32", 10, 21)
+GEN_TWOVEC_TEST(scvtf_d_d_fbits64, "scvtf d10, d21 , #64", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_d_d_fbits1, "ucvtf d21, d10 , #1", 21, 10)
+GEN_TWOVEC_TEST(ucvtf_d_d_fbits32, "ucvtf d21, d10 , #32", 21, 10)
+GEN_TWOVEC_TEST(ucvtf_d_d_fbits64, "ucvtf d21, d10 , #64", 21, 10)
+GEN_TWOVEC_TEST(scvtf_s_s_fbits1, "scvtf s10, s21 , #1", 10, 21)
+GEN_TWOVEC_TEST(scvtf_s_s_fbits16, "scvtf s10, s21 , #16", 10, 21)
+GEN_TWOVEC_TEST(scvtf_s_s_fbits32, "scvtf s10, s21 , #32", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_s_s_fbits1, "ucvtf s21, s10 , #1", 21, 10)
+GEN_TWOVEC_TEST(ucvtf_s_s_fbits16, "ucvtf s21, s10 , #16", 21, 10)
+GEN_TWOVEC_TEST(ucvtf_s_s_fbits32, "ucvtf s21, s10 , #32", 21, 10)
+GEN_TWOVEC_TEST(scvtf_2d_2d_fbits1, "scvtf v10.2d, v21.2d, #1", 10, 21)
+GEN_TWOVEC_TEST(scvtf_2d_2d_fbits32, "scvtf v10.2d, v21.2d, #32", 10, 21)
+GEN_TWOVEC_TEST(scvtf_2d_2d_fbits64, "scvtf v10.2d, v21.2d, #64", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2d_2d_fbits1, "ucvtf v10.2d, v21.2d, #1", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2d_2d_fbits32, "ucvtf v10.2d, v21.2d, #32", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2d_2d_fbits64, "ucvtf v10.2d, v21.2d, #64", 10, 21)
+GEN_TWOVEC_TEST(scvtf_4s_4s_fbits1, "scvtf v10.4s, v21.4s, #1", 10, 21)
+GEN_TWOVEC_TEST(scvtf_4s_4s_fbits16, "scvtf v10.4s, v21.4s, #16", 10, 21)
+GEN_TWOVEC_TEST(scvtf_4s_4s_fbits32, "scvtf v10.4s, v21.4s, #32", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_4s_4s_fbits1, "ucvtf v10.4s, v21.4s, #1", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_4s_4s_fbits16, "ucvtf v10.4s, v21.4s, #16", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_4s_4s_fbits32, "ucvtf v10.4s, v21.4s, #32", 10, 21)
+GEN_TWOVEC_TEST(scvtf_2s_2s_fbits1, "scvtf v10.2s, v21.2s, #1", 10, 21)
+GEN_TWOVEC_TEST(scvtf_2s_2s_fbits16, "scvtf v10.2s, v21.2s, #16", 10, 21)
+GEN_TWOVEC_TEST(scvtf_2s_2s_fbits32, "scvtf v10.2s, v21.2s, #32", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2s_2s_fbits1, "ucvtf v10.2s, v21.2s, #1", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2s_2s_fbits16, "ucvtf v10.2s, v21.2s, #16", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2s_2s_fbits32, "ucvtf v10.2s, v21.2s, #32", 10, 21)
+
+GEN_TWOVEC_TEST(scvtf_d_d, "scvtf d10, d21", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_d_d, "ucvtf d21, d10", 21, 10)
+GEN_TWOVEC_TEST(scvtf_s_s, "scvtf s10, s21", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_s_s, "ucvtf s21, s10", 21, 10)
+GEN_TWOVEC_TEST(scvtf_2d_2d, "scvtf v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2d_2d, "ucvtf v10.2d, v21.2d", 10, 21)
+GEN_TWOVEC_TEST(scvtf_4s_4s, "scvtf v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_4s_4s, "ucvtf v10.4s, v21.4s", 10, 21)
+GEN_TWOVEC_TEST(scvtf_2s_2s, "scvtf v10.2s, v21.2s", 10, 21)
+GEN_TWOVEC_TEST(ucvtf_2s_2s, "ucvtf v10.2s, v21.2s", 10, 21)
+
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_w_fbits1, "scvtf s7, w15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_w_fbits16, "scvtf s7, w15, #16", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_w_fbits32, "scvtf s7, w15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_w_fbits1, "scvtf d7, w15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_w_fbits16, "scvtf d7, w15, #16", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_w_fbits32, "scvtf d7, w15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_x_fbits1, "scvtf s7, x15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_x_fbits32, "scvtf s7, x15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_x_fbits64, "scvtf s7, x15, #64", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_x_fbits1, "scvtf d7, x15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_x_fbits32, "scvtf d7, x15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_x_fbits64, "scvtf d7, x15, #64", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w_fbits1, "ucvtf s7, w15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w_fbits16, "ucvtf s7, w15, #16", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w_fbits32, "ucvtf s7, w15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w_fbits1, "ucvtf d7, w15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w_fbits16, "ucvtf d7, w15, #16", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w_fbits32, "ucvtf d7, w15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x_fbits1, "ucvtf s7, x15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x_fbits32, "ucvtf s7, x15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x_fbits64, "ucvtf s7, x15, #64", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x_fbits1, "ucvtf d7, x15, #1", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x_fbits32, "ucvtf d7, x15, #32", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x_fbits64, "ucvtf d7, x15, #64", 15, 7)
GEN_ONEINT_ONEVEC_TEST(scvtf_s_w, "scvtf s7, w15", 15, 7)
GEN_ONEINT_ONEVEC_TEST(scvtf_d_w, "scvtf d7, w15", 15, 7)
@@ -4357,6 +4526,34 @@
GEN_UNARY_TEST(xtn, 8b, 8h)
GEN_UNARY_TEST(xtn2, 16b, 8h)
+// ======================== MEM ========================
+
+// All the SIMD and FP memory tests are in none/tests/arm64/memory.c.
+
+// ======================== CRYPTO ========================
+
+// These tests are believed to be correct but are disabled because
+// GNU assembler (GNU Binutils) 2.24.0.20140311 Linaro 2014.03
+// cannot be persuaded to accept those instructions (AFAICT).
+
+//GEN_TWOVEC_TEST(aesd_16b_16b, "aesd v6.16b, v27.16b", 6, 27)
+//GEN_TWOVEC_TEST(aese_16b_16b, "aese v6.16b, v27.16b", 6, 27)
+//GEN_TWOVEC_TEST(aesimc_16b_16b, "aesimc v6.16b, v27.16b", 6, 27)
+//GEN_TWOVEC_TEST(aesmc_16b_16b, "aesmc v6.16b, v27.16b", 6, 27)
+//
+//GEN_THREEVEC_TEST(sha1c_q_s_4s, "sha1c q29, s28, v27.4s", 29,28,27)
+//GEN_TWOVEC_TEST(sha1h_s_s, "sha1h s6, s27", 6, 27)
+//GEN_THREEVEC_TEST(sha1m_q_s_4s, "sha1m q29, s28, v27.4s", 29,28,27)
+//GEN_THREEVEC_TEST(sha1p_q_s_4s, "sha1p q29, s28, v27.4s", 29,28,27)
+//GEN_THREEVEC_TEST(sha1su0_4s_4s_4s, "sha1su0 v29.4s, v28.4s, v27.4s", 29,28,27)
+//GEN_TWOVEC_TEST(sha1su1_4s_4s, "sha1su1 v6.4s, v27.4s", 6, 27)
+//
+//GEN_THREEVEC_TEST(sha256h2_q_q_4s, "sha256h2 q29, q28, v27.4s", 29,28,27)
+//GEN_THREEVEC_TEST(sha256h_q_q_4s, "sha256h q29, q28, v27.4s", 29,28,27)
+//GEN_TWOVEC_TEST(sha256su0_4s_4s, "sha256su0 v6.4s, v27.4s", 6, 27)
+//GEN_THREEVEC_TEST(sha256su1_4s_4s_4s, "sha256su1 v29.4s, v28.4s, v27.4s",
+// 29,28,27)
+
/* ---------------------------------------------------------------- */
/* -- main() -- */
@@ -4531,10 +4728,10 @@
if (0) DO50( test_FCMPE_S_S() );
// fcsel d,s (fp cond select)
- if (0) DO50( test_FCSEL_D_D_D_EQ() );
- if (0) DO50( test_FCSEL_D_D_D_NE() );
- if (0) DO50( test_FCSEL_S_S_S_EQ() );
- if (0) DO50( test_FCSEL_S_S_S_NE() );
+ if (1) DO50( test_FCSEL_D_D_D_EQ() );
+ if (1) DO50( test_FCSEL_D_D_D_NE() );
+ if (1) DO50( test_FCSEL_S_S_S_EQ() );
+ if (1) DO50( test_FCSEL_S_S_S_NE() );
// fdiv d,s
// fdiv 2d,4s,2s
@@ -4832,13 +5029,24 @@
// ======================== CONV ========================
// fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
+ if (0) test_fcvt_s_h(TyHF);
+ if (0) test_fcvt_d_h(TyHF);
+ if (0) test_fcvt_h_s(TySF);
+ if (0) test_fcvt_d_s(TySF);
+ if (0) test_fcvt_h_d(TyDF);
+ if (0) test_fcvt_s_d(TyDF);
// fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
+ if (0) test_fcvtl_4s_4h(TyHF);
+ if (0) test_fcvtl_4s_8h(TyHF);
+ if (0) test_fcvtl_2d_2s(TySF);
+ if (0) test_fcvtl_2d_4s(TySF);
// fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
- // INCOMPLETE
- if (1) test_fcvtn_2s_2d(TyDF);
- if (1) test_fcvtn_4s_2d(TyDF);
+ if (0) test_fcvtn_4h_4s(TySF);
+ if (0) test_fcvtn_8h_4s(TySF);
+ if (0) test_fcvtn_2s_2d(TyDF);
+ if (0) test_fcvtn_4s_2d(TyDF);
// fcvtas d,s (fcvt to signed int, nearest, ties away)
// fcvtau d,s (fcvt to unsigned int, nearest, ties away)
@@ -4846,6 +5054,24 @@
// fcvtau 2d,4s,2s
// fcvtas w_s,x_s,w_d,x_d
// fcvtau w_s,x_s,w_d,x_d
+ if (0) test_fcvtas_d_d(TyDF);
+ if (0) test_fcvtau_d_d(TyDF);
+ if (0) test_fcvtas_s_s(TySF);
+ if (0) test_fcvtau_s_s(TySF);
+ if (0) test_fcvtas_2d_2d(TyDF);
+ if (0) test_fcvtau_2d_2d(TyDF);
+ if (0) test_fcvtas_4s_4s(TySF);
+ if (0) test_fcvtau_4s_4s(TySF);
+ if (0) test_fcvtas_2s_2s(TySF);
+ if (0) test_fcvtau_2s_2s(TySF);
+ if (0) test_fcvtas_w_s(TySF);
+ if (0) test_fcvtau_w_s(TySF);
+ if (0) test_fcvtas_x_s(TySF);
+ if (0) test_fcvtau_x_s(TySF);
+ if (0) test_fcvtas_w_d(TyDF);
+ if (0) test_fcvtau_w_d(TyDF);
+ if (0) test_fcvtas_x_d(TyDF);
+ if (0) test_fcvtau_x_d(TyDF);
// fcvtms d,s (fcvt to signed int, minus inf)
// fcvtmu d,s (fcvt to unsigned int, minus inf)
@@ -4853,6 +5079,24 @@
// fcvtmu 2d,4s,2s
// fcvtms w_s,x_s,w_d,x_d
// fcvtmu w_s,x_s,w_d,x_d
+ if (0) test_fcvtms_d_d(TyDF);
+ if (0) test_fcvtmu_d_d(TyDF);
+ if (0) test_fcvtms_s_s(TySF);
+ if (0) test_fcvtmu_s_s(TySF);
+ if (0) test_fcvtms_2d_2d(TyDF);
+ if (0) test_fcvtmu_2d_2d(TyDF);
+ if (0) test_fcvtms_4s_4s(TySF);
+ if (0) test_fcvtmu_4s_4s(TySF);
+ if (0) test_fcvtms_2s_2s(TySF);
+ if (0) test_fcvtmu_2s_2s(TySF);
+ if (0) test_fcvtms_w_s(TySF);
+ if (0) test_fcvtmu_w_s(TySF);
+ if (0) test_fcvtms_x_s(TySF);
+ if (0) test_fcvtmu_x_s(TySF);
+ if (0) test_fcvtms_w_d(TyDF);
+ if (0) test_fcvtmu_w_d(TyDF);
+ if (0) test_fcvtms_x_d(TyDF);
+ if (0) test_fcvtmu_x_d(TyDF);
// fcvtns d,s (fcvt to signed int, nearest)
// fcvtnu d,s (fcvt to unsigned int, nearest)
@@ -4860,6 +5104,24 @@
// fcvtnu 2d,4s,2s
// fcvtns w_s,x_s,w_d,x_d
// fcvtnu w_s,x_s,w_d,x_d
+ if (0) test_fcvtns_d_d(TyDF);
+ if (0) test_fcvtnu_d_d(TyDF);
+ if (0) test_fcvtns_s_s(TySF);
+ if (0) test_fcvtnu_s_s(TySF);
+ if (0) test_fcvtns_2d_2d(TyDF);
+ if (0) test_fcvtnu_2d_2d(TyDF);
+ if (0) test_fcvtns_4s_4s(TySF);
+ if (0) test_fcvtnu_4s_4s(TySF);
+ if (0) test_fcvtns_2s_2s(TySF);
+ if (0) test_fcvtnu_2s_2s(TySF);
+ if (0) test_fcvtns_w_s(TySF);
+ if (0) test_fcvtnu_w_s(TySF);
+ if (0) test_fcvtns_x_s(TySF);
+ if (0) test_fcvtnu_x_s(TySF);
+ if (0) test_fcvtns_w_d(TyDF);
+ if (0) test_fcvtnu_w_d(TyDF);
+ if (0) test_fcvtns_x_d(TyDF);
+ if (0) test_fcvtnu_x_d(TyDF);
// fcvtps d,s (fcvt to signed int, plus inf)
// fcvtpu d,s (fcvt to unsigned int, plus inf)
@@ -4867,6 +5129,24 @@
// fcvtpu 2d,4s,2s
// fcvtps w_s,x_s,w_d,x_d
// fcvtpu w_s,x_s,w_d,x_d
+ if (0) test_fcvtps_d_d(TyDF);
+ if (0) test_fcvtpu_d_d(TyDF);
+ if (0) test_fcvtps_s_s(TySF);
+ if (0) test_fcvtpu_s_s(TySF);
+ if (0) test_fcvtps_2d_2d(TyDF);
+ if (0) test_fcvtpu_2d_2d(TyDF);
+ if (0) test_fcvtps_4s_4s(TySF);
+ if (0) test_fcvtpu_4s_4s(TySF);
+ if (0) test_fcvtps_2s_2s(TySF);
+ if (0) test_fcvtpu_2s_2s(TySF);
+ if (0) test_fcvtps_w_s(TySF);
+ if (0) test_fcvtpu_w_s(TySF);
+ if (0) test_fcvtps_x_s(TySF);
+ if (0) test_fcvtpu_x_s(TySF);
+ if (0) test_fcvtps_w_d(TyDF);
+ if (0) test_fcvtpu_w_d(TyDF);
+ if (0) test_fcvtps_x_d(TyDF);
+ if (0) test_fcvtpu_x_d(TyDF);
// fcvtzs d,s (fcvt to signed integer, to zero)
// fcvtzu d,s (fcvt to unsigned integer, to zero)
@@ -4874,31 +5154,168 @@
// fcvtzu 2d,4s,2s
// fcvtzs w_s,x_s,w_d,x_d
// fcvtzu w_s,x_s,w_d,x_d
+ if (0) test_fcvtzs_d_d(TyDF);
+ if (0) test_fcvtzu_d_d(TyDF);
+ if (0) test_fcvtzs_s_s(TySF);
+ if (0) test_fcvtzu_s_s(TySF);
+ if (0) test_fcvtzs_2d_2d(TyDF);
+ if (0) test_fcvtzu_2d_2d(TyDF);
+ if (0) test_fcvtzs_4s_4s(TySF);
+ if (0) test_fcvtzu_4s_4s(TySF);
+ if (0) test_fcvtzs_2s_2s(TySF);
+ if (0) test_fcvtzu_2s_2s(TySF);
+ if (0) test_fcvtzs_w_s(TySF);
+ if (0) test_fcvtzu_w_s(TySF);
+ if (0) test_fcvtzs_x_s(TySF);
+ if (0) test_fcvtzu_x_s(TySF);
+ if (0) test_fcvtzs_w_d(TyDF);
+ if (0) test_fcvtzu_w_d(TyDF);
+ if (0) test_fcvtzs_x_d(TyDF);
+ if (0) test_fcvtzu_x_d(TyDF);
// fcvtzs d,s (fcvt to signed fixedpt, to zero) (w/ #fbits)
// fcvtzu d,s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
- // fcvtzs 2d,4s,2s
- // fcvtzu 2d,4s,2s
+ // fcvtzs 2d,4s,2s (fcvt to signed fixedpt, to zero) (w/ #fbits)
+ // fcvtzu 2d,4s,2s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
// fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits)
// fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
+ if (0) test_fcvtzs_d_d_fbits1(TyDF);
+ if (0) test_fcvtzs_d_d_fbits32(TyDF);
+ if (0) test_fcvtzs_d_d_fbits64(TyDF);
+ if (0) test_fcvtzu_d_d_fbits1(TyDF);
+ if (0) test_fcvtzu_d_d_fbits32(TyDF);
+ if (0) test_fcvtzu_d_d_fbits64(TyDF);
+ if (0) test_fcvtzs_s_s_fbits1(TySF);
+ if (0) test_fcvtzs_s_s_fbits16(TySF);
+ if (0) test_fcvtzs_s_s_fbits32(TySF);
+ if (0) test_fcvtzu_s_s_fbits1(TySF);
+ if (0) test_fcvtzu_s_s_fbits16(TySF);
+ if (0) test_fcvtzu_s_s_fbits32(TySF);
+ if (0) test_fcvtzs_2d_2d_fbits1(TyDF);
+ if (0) test_fcvtzs_2d_2d_fbits32(TyDF);
+ if (0) test_fcvtzs_2d_2d_fbits64(TyDF);
+ if (0) test_fcvtzu_2d_2d_fbits1(TyDF);
+ if (0) test_fcvtzu_2d_2d_fbits32(TyDF);
+ if (0) test_fcvtzu_2d_2d_fbits64(TyDF);
+ if (0) test_fcvtzs_4s_4s_fbits1(TySF);
+ if (0) test_fcvtzs_4s_4s_fbits16(TySF);
+ if (0) test_fcvtzs_4s_4s_fbits32(TySF);
+ if (0) test_fcvtzu_4s_4s_fbits1(TySF);
+ if (0) test_fcvtzu_4s_4s_fbits16(TySF);
+ if (0) test_fcvtzu_4s_4s_fbits32(TySF);
+ if (0) test_fcvtzs_2s_2s_fbits1(TySF);
+ if (0) test_fcvtzs_2s_2s_fbits16(TySF);
+ if (0) test_fcvtzs_2s_2s_fbits32(TySF);
+ if (0) test_fcvtzu_2s_2s_fbits1(TySF);
+ if (0) test_fcvtzu_2s_2s_fbits16(TySF);
+ if (0) test_fcvtzu_2s_2s_fbits32(TySF);
+ if (0) test_fcvtzs_w_s_fbits1(TySF);
+ if (0) test_fcvtzs_w_s_fbits16(TySF);
+ if (0) test_fcvtzs_w_s_fbits32(TySF);
+ if (0) test_fcvtzu_w_s_fbits1(TySF);
+ if (0) test_fcvtzu_w_s_fbits16(TySF);
+ if (0) test_fcvtzu_w_s_fbits32(TySF);
+ if (0) test_fcvtzs_x_s_fbits1(TySF);
+ if (0) test_fcvtzs_x_s_fbits32(TySF);
+ if (0) test_fcvtzs_x_s_fbits64(TySF);
+ if (0) test_fcvtzu_x_s_fbits1(TySF);
+ if (0) test_fcvtzu_x_s_fbits32(TySF);
+ if (0) test_fcvtzu_x_s_fbits64(TySF);
+ if (0) test_fcvtzs_w_d_fbits1(TyDF);
+ if (0) test_fcvtzs_w_d_fbits16(TyDF);
+ if (0) test_fcvtzs_w_d_fbits32(TyDF);
+ if (0) test_fcvtzu_w_d_fbits1(TyDF);
+ if (0) test_fcvtzu_w_d_fbits16(TyDF);
+ if (0) test_fcvtzu_w_d_fbits32(TyDF);
+ if (0) test_fcvtzs_x_d_fbits1(TyDF);
+ if (0) test_fcvtzs_x_d_fbits32(TyDF);
+ if (0) test_fcvtzs_x_d_fbits64(TyDF);
+ if (0) test_fcvtzu_x_d_fbits1(TyDF);
+ if (0) test_fcvtzu_x_d_fbits32(TyDF);
+ if (0) test_fcvtzu_x_d_fbits64(TyDF);
// fcvtxn s_d (fcvt to lower prec narrow, rounding to odd)
// fcvtxn 2s_2d,4s_2d
+ if (0) test_fcvtxn_s_d(TyDF);
+ if (0) test_fcvtxn_2s_2d(TyDF);
+ if (0) test_fcvtxn_4s_2d(TyDF);
// scvtf d,s _#fbits
// ucvtf d,s _#fbits
-
// scvtf 2d,4s,2s _#fbits
// ucvtf 2d,4s,2s _#fbits
+ if (0) test_scvtf_d_d_fbits1(TyD);
+ if (0) test_scvtf_d_d_fbits32(TyD);
+ if (0) test_scvtf_d_d_fbits64(TyD);
+ if (0) test_ucvtf_d_d_fbits1(TyD);
+ if (0) test_ucvtf_d_d_fbits32(TyD);
+ if (0) test_ucvtf_d_d_fbits64(TyD);
+ if (0) test_scvtf_s_s_fbits1(TyS);
+ if (0) test_scvtf_s_s_fbits16(TyS);
+ if (0) test_scvtf_s_s_fbits32(TyS);
+ if (0) test_ucvtf_s_s_fbits1(TyS);
+ if (0) test_ucvtf_s_s_fbits16(TyS);
+ if (0) test_ucvtf_s_s_fbits32(TyS);
+ if (0) test_scvtf_2d_2d_fbits1(TyD);
+ if (0) test_scvtf_2d_2d_fbits32(TyD);
+ if (0) test_scvtf_2d_2d_fbits64(TyD);
+ if (0) test_ucvtf_2d_2d_fbits1(TyD);
+ if (0) test_ucvtf_2d_2d_fbits32(TyD);
+ if (0) test_ucvtf_2d_2d_fbits64(TyD);
+ if (0) test_scvtf_4s_4s_fbits1(TyS);
+ if (0) test_scvtf_4s_4s_fbits16(TyS);
+ if (0) test_scvtf_4s_4s_fbits32(TyS);
+ if (0) test_ucvtf_4s_4s_fbits1(TyS);
+ if (0) test_ucvtf_4s_4s_fbits16(TyS);
+ if (0) test_ucvtf_4s_4s_fbits32(TyS);
+ if (0) test_scvtf_2s_2s_fbits1(TyS);
+ if (0) test_scvtf_2s_2s_fbits16(TyS);
+ if (0) test_scvtf_2s_2s_fbits32(TyS);
+ if (0) test_ucvtf_2s_2s_fbits1(TyS);
+ if (0) test_ucvtf_2s_2s_fbits16(TyS);
+ if (0) test_ucvtf_2s_2s_fbits32(TyS);
// scvtf d,s
// ucvtf d,s
-
// scvtf 2d,4s,2s
// ucvtf 2d,4s,2s
+ if (0) test_scvtf_d_d(TyD);
+ if (0) test_ucvtf_d_d(TyD);
+ if (0) test_scvtf_s_s(TyS);
+ if (0) test_ucvtf_s_s(TyS);
+ if (0) test_scvtf_2d_2d(TyD);
+ if (0) test_ucvtf_2d_2d(TyD);
+ if (0) test_scvtf_4s_4s(TyS);
+ if (0) test_ucvtf_4s_4s(TyS);
+ if (0) test_scvtf_2s_2s(TyS);
+ if (0) test_ucvtf_2s_2s(TyS);
// scvtf s_w, d_w, s_x, d_x, _#fbits
// ucvtf s_w, d_w, s_x, d_x, _#fbits
+ if (0) test_scvtf_s_w_fbits1(TyS);
+ if (0) test_scvtf_s_w_fbits16(TyS);
+ if (0) test_scvtf_s_w_fbits32(TyS);
+ if (0) test_scvtf_d_w_fbits1(TyS);
+ if (0) test_scvtf_d_w_fbits16(TyS);
+ if (0) test_scvtf_d_w_fbits32(TyS);
+ if (0) test_scvtf_s_x_fbits1(TyD);
+ if (0) test_scvtf_s_x_fbits32(TyD);
+ if (0) test_scvtf_s_x_fbits64(TyD);
+ if (0) test_scvtf_d_x_fbits1(TyD);
+ if (0) test_scvtf_d_x_fbits32(TyD);
+ if (0) test_scvtf_d_x_fbits64(TyD);
+ if (0) test_ucvtf_s_w_fbits1(TyS);
+ if (0) test_ucvtf_s_w_fbits16(TyS);
+ if (0) test_ucvtf_s_w_fbits32(TyS);
+ if (0) test_ucvtf_d_w_fbits1(TyS);
+ if (0) test_ucvtf_d_w_fbits16(TyS);
+ if (0) test_ucvtf_d_w_fbits32(TyS);
+ if (0) test_ucvtf_s_x_fbits1(TyD);
+ if (0) test_ucvtf_s_x_fbits32(TyD);
+ if (0) test_ucvtf_s_x_fbits64(TyD);
+ if (0) test_ucvtf_d_x_fbits1(TyD);
+ if (0) test_ucvtf_d_x_fbits32(TyD);
+ if (0) test_ucvtf_d_x_fbits64(TyD);
// scvtf s_w, d_w, s_x, d_x
// ucvtf s_w, d_w, s_x, d_x
@@ -6913,6 +7330,8 @@
// ======================== MEM ========================
+ // All the SIMD and FP memory tests are in none/tests/arm64/memory.c.
+
// ld1 (multiple 1-element structures to 1/2/3/4 regs)
// ld1 (single 1-element structure to one lane of 1 reg)
// ld1r (single 1-element structure and rep to all lanes of 1 reg)
@@ -6975,10 +7394,18 @@
// ======================== CRYPTO ========================
+ // These tests are believed to be correct but are disabled because
+ // GNU assembler (GNU Binutils) 2.24.0.20140311 Linaro 2014.03
+ // cannot be persuaded to accept those instructions (AFAICT).
+
// aesd 16b (aes single round decryption)
// aese 16b (aes single round encryption)
// aesimc 16b (aes inverse mix columns)
// aesmc 16b (aes mix columns)
+ //if (0) test_aesd_16b_16b(TyNONE);
+ //if (0) test_aese_16b_16b(TyNONE);
+ //if (0) test_aesimc_16b_16b(TyNONE);
+ //if (0) test_aesmc_16b_16b(TyNONE);
// sha1c q_s_4s
// sha1h s_s
@@ -6986,11 +7413,21 @@
// sha1p q_s_4s
// sha1su0 4s_4s_4s
// sha1su1 4s_4s
+ //if (0) test_sha1c_q_s_4s(TyNONE);
+ //if (0) test_sha1h_s_s(TyNONE);
+ //if (0) test_sha1m_q_s_4s(TyNONE);
+ //if (0) test_sha1p_q_s_4s(TyNONE);
+ //if (0) test_sha1su0_4s_4s_4s(TyNONE);
+ //if (0) test_sha1su1_4s_4s(TyNONE);
// sha256h2 q_q_4s
// sha256h q_q_4s
// sha256su0 4s_4s
// sha256su1 4s_4s_4s
+ //if (0) test_sha256h2_q_q_4s(TyNONE);
+ //if (0) test_sha256h_q_q_4s(TyNONE);
+ //if (0) test_sha256su0_4s_4s(TyNONE);
+ //if (0) test_sha256su1_4s_4s_4s(TyNONE);
return 0;
}
Modified: trunk/none/tests/arm64/fp_and_simd.stdout.exp
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.stdout.exp (original)
+++ trunk/none/tests/arm64/fp_and_simd.stdout.exp Sat Nov 15 22:15:47 2014
@@ -40,1950 +40,4160 @@
facgt v2.2d, v23.2d, v11.2d 9c727edf66767ca38fe6d7c56a5ff965 579f90d5d9cd1c3afceebf50e0d0ba24 761b274ac4c4f0c7f31ed81010c417bc 0000000000000000ffffffffffffffff 579f90d5d9cd1c3afceebf50e0d0ba24 761b274ac4c4f0c7f31ed81010c417bc fpsr=00000000
facgt v2.4s, v23.4s, v11.4s 25c80a060da03fb0c33ebc4b44b8ddd8 5791e2f2a78f37627c9fe23c60c5d82b b3633c2f304791cde6c097130b5efcf6 ffffffff00000000ffffffffffffffff 5791e2f2a78f37627c9fe23c60c5d82b b3633c2f304791cde6c097130b5efcf6 fpsr=00000000
facgt v2.2s, v23.2s, v11.2s 0e1d55b9c001d4c793aee0cffbdea09a 84db9fe3e4b100d48d969e225f9318a0 04b4378bce1492e08680a7399beeae16 0000000000000000ffffffffffffffff 84db9fe3e4b100d48d969e225f9318a0 04b4378bce1492e08680a7399beeae16 fpsr=00000000
-fdiv d2, d11, d29 2e467d8e98e7468c75a0cbeda561e618 9c86e5cb54c594021c25022200a7415e 1adad8978cbfb47829861f0d48dc87f5 0000000000000000328e63d83c3e7d7f 9c86e5cb54c594021c25022200a7415e 1adad8978cbfb47829861f0d48dc87f5 fpsr=00000000
-fdiv s2, s11, s29 b168a24af5479e7bc9f1d5f8e2de4bd3 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 0000000000000000000000005944d419 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 fpsr=00000000
-fdiv v9.2d, v7.2d, v8.2d 07121ecd88441b7dd2cc3eca9347d80f 6e1d4703bf5de53fd97270f257c73303 00000000000000003948819912cd8273 fpsr=00000000
-fdiv v9.4s, v7.4s, v8.4s 077815d35567232e66c997070e860c39 109cfa471afbe686e2ede96f8809f947 364a4a1579eae627c358eaa6c5f8b732 fpsr=00000000
-fdiv v9.2s, v7.2s, v8.2s 462deabeada6093241150c7a1a4df892 89ad76dc21a1f8f15acd7ad9f991bada 000000000000000025b9b1c980000000 fpsr=00000000
-fnmul d2, d11, d29 2a1f00ed91e9071d79112f6f64f5079c df63bd3c7359f634f791559ff8d88161 fba1981add7938e3067d74917c37833e 00000000000000003e1fe97c596207a3 df63bd3c7359f634f791559ff8d88161 fba1981add7938e3067d74917c37833e fpsr=00000000
-fnmul s2, s11, s29 9cdd1a32cd007ff7daac12cf3a64acbd e76fcc086aeb0414a9cd126c0869c6a0 d973ba438b80fdb556878af3ad4a4cb8 00000000000000000000000000000006 e76fcc086aeb0414a9cd126c0869c6a0 d973ba438b80fdb556878af3ad4a4cb8 fpsr=00000000
-fmla v2.2d, v23.2d, v11.2d fa0ba48e9db3d6f2c0c135e244f24dfe 71a4885bc70f501cf18441c67d4b9e45 95a6e59e2a7fabcb65b86284a1cb27a3 fa0ba48e9db3d6f2fff0000000000000 71a4885bc70f501cf18441c67d4b9e45 95a6e59e2a7fabcb65b86284a1cb27a3 fpsr=00000000
-fmla v2.4s, v23.4s, v11.4s aef4eeb358364f4add55d3bb09c439c9 3028339e0d3a0c468e8f584ceae94e7a e33fad8f313a964967940f284cfce9a3 d3fbe11758364f4add55d3bbf8667e2d 3028339e0d3a0c468e8f584ceae94e7a e33fad8f313a964967940f284cfce9a3 fpsr=00000000
-fmla v2.2s, v23.2s, v11.2s 6c9a8e07714d3d2264ecfe407d2043c1 d6006035af2e8bb7b3736be34585abe2 7742a77a117513548f9ea7c3a323665c 000000000000000064ecfe407d2043c1 d6006035af2e8bb7b3736be34585abe2 7742a77a117513548f9ea7c3a323665c fpsr=00000000
-randV128: 256 calls, 266 iters
-fmls v2.2d, v23.2d, v11.2d e70216ec5cbcf49e8a09cb539549408a 182fa58322b1219295b48e6f81658922 05b265c33ff4760f125b3d3899837173 e70216ec5cbcf49e8a09cb539549408a 182fa58322b1219295b48e6f81658922 05b265c33ff4760f125b3d3899837173 fpsr=00000000
-fmls v2.4s, v23.4s, v11.4s aaba95edd88623fc68d5d5d393ccbadd 40947ccd307b129e244ee56d2260de8c d2b5bf6419898df003e6fe7283eff6cb 53d2d680d88623fc68d5d5d393ccbadd 40947ccd307b129e244ee56d2260de8c d2b5bf6419898df003e6fe7283eff6cb fpsr=00000000
-fmls v2.2s, v23.2s, v11.2s 3fa5c4d84771e518605a54f56dfe15b7 ddeb80fe57ce3c26f9fcb34432fe8249 3b3296ac6d6e4ba4d95578b09e02700d 0000000000000000ff8000006dfe15b7 ddeb80fe57ce3c26f9fcb34432fe8249 3b3296ac6d6e4ba4d95578b09e02700d fpsr=00000000
-fmla v2.2d, v11.2d, v29.d[0] 8fbc05b829b247cac4e8bba2bda13050 98bf1ba36919393bc4d999db7390839e 44d5584589abea635dc49b10189f4c14 b6940803a6f62057e2b07c3747d2a5f7 98bf1ba36919393bc4d999db7390839e 44d5584589abea635dc49b10189f4c14 fpsr=00000000
-fmla v2.2d, v11.2d, v29.d[1] 0b0b9f6018e987aeba97106bb88dbd45 9d5fe4af824eabd8f8f577d6f4dd0223 d6c08bc57f47f9ba34279d2f35968b0a 34307da5f2392ab27ff0000000000000 9d5fe4af824eabd8f8f577d6f4dd0223 d6c08bc57f47f9ba34279d2f35968b0a fpsr=00000000
-fmla v2.4s, v11.4s, v29.s[0] 05dbe25a9a3951f70e8dc8821606fcca fe1783322bd1f4a0a92e2587172ec23f 22d9446284e6ae8126fc5ee9b286181e 711eb9e49edc50501c3670191606fcc9 fe1783322bd1f4a0a92e2587172ec23f 22d9446284e6ae8126fc5ee9b286181e fpsr=00000000
-fmla v2.4s, v11.4s, v29.s[3] 3131620a2265f8c8f64df6cdcb51c286 6eeb8d90d86668b60a08b6d0cfc59797 dc2316810c4e5ddd66c8f02281b3c8f2 ff8000007512c8edf64df6cd6c7bc1c7 6eeb8d90d86668b60a08b6d0cfc59797 dc2316810c4e5ddd66c8f02281b3c8f2 fpsr=00000000
-fmla v2.2s, v11.2s, v29.s[0] 4210b3d32431d146a45cad2eccb0e21a a2de962ffdd15c3e50063f9610e753cd b7a39486894259f1290e68be98626e2d 0000000000000000a8edea2accb0e21a a2de962ffdd15c3e50063f9610e753cd b7a39486894259f1290e68be98626e2d fpsr=00000000
-fmla v2.2s, v11.2s, v29.s[3] ee7d691b146130944d3d038a0b69312c 4df433720fd7245dafacd5bdced9cd88 685c54d57186f6e2a353dba0ead5df70 0000000000000000d894c0f3f7bb74ce 4df433720fd7245dafacd5bdced9cd88 685c54d57186f6e2a353dba0ead5df70 fpsr=00000000
-fmls v2.2d, v11.2d, v29.d[0] e77b184466b967d624750ac67ebe825f 2533f6bc813a13365b808a28feded669 a353e8d137de89d3071b5bad6b52ee61 e77b184466b967d624750ac67ddc430d 2533f6bc813a13365b808a28feded669 a353e8d137de89d3071b5bad6b52ee61 fpsr=00000000
-fmls v2.2d, v11.2d, v29.d[1] e11053b38ffdcd305e88d8c318f5aa57 dc9d7472c7c07dee870474bd92394516 1b8ce6e04f0e66e88ae9fdca101c70a3 e11053b38ffdcd305e88d8c318f5aa57 dc9d7472c7c07dee870474bd92394516 1b8ce6e04f0e66e88ae9fdca101c70a3 fpsr=00000000
-fmls v2.4s, v11.4s, v29.s[0] 913db0cc02f1b3c72ff97f68cd517cb9 850ae0642ddae0466041d5d9cb7738db 2af3bd4b509e6608a513cfe482162be8 913db0cc02f1b3c72ff97f68cd517cb9 850ae0642ddae0466041d5d9cb7738db 2af3bd4b509e6608a513cfe482162be8 fpsr=00000000
-fmls v2.4s, v11.4s, v29.s[3] b903f1b29f411487312d32f1bb069e61 95d26cc246074b10bda9f7bf92a71bac fcefa19f2c8a8cfd3989634f2a294a7c d344f8627f800000fb1f199ad01c6c56 95d26cc246074b10bda9f7bf92a71bac fcefa19f2c8a8cfd3989634f2a294a7c fpsr=00000000
-fmls v2.2s, v11.2s, v29.s[0] 470818041ac5e9b218db305838ff3248 06ced856b4d04648a668c3da0fcbe652 39d4db0931b25e927a9632b68f624628 000000000000000018db305838ff3248 06ced856b4d04648a668c3da0fcbe652 39d4db0931b25e927a9632b68f624628 fpsr=00000000
-fmls v2.2s, v11.2s, v29.s[3] 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 32746a5ace2a448f4d76dd08966fd815 0000000000000000dab3699f98380582 fc95f5d55c34e70e2034036b2540d210 32746a5ace2a448f4d76dd08966fd815 fpsr=00000000
-fmov v22.2d, #0.125 b00b3cdf75747e60035ee161b2ddaa1e 92478e7f987ac472db7137e460cce35a 3fc00000000000003fc0000000000000 92478e7f987ac472db7137e460cce35a fpsr=00000000
-fmov v22.2d, #-4.0 45aeabe876d3472e35c647934c948f3a e08c1f71338e7c577f778f72bc6577b1 c010000000000000c010000000000000 e08c1f71338e7c577f778f72bc6577b1 fpsr=00000000
-fmov v22.2d, #1.0 ded3251e3f2e1bf337f62011aebf77d2 fbc9f1302bfc1b23d243aed4a862c488 3ff00000000000003ff0000000000000 fbc9f1302bfc1b23d243aed4a862c488 fpsr=00000000
-fmov d22, d23 6c7f80e89ebd80a5e34bca20163ac21e e06c5cc8e1357d72cece7967d1f50cd5 0000000000000000cece7967d1f50cd5 e06c5cc8e1357d72cece7967d1f50cd5 fpsr=00000000
-fmov s22, s23 6aed102f2e988dcd62d86d00d43737f5 ed6bf4b500d2fe8f552735a28721f705 0000000000000000000000008721f705 ed6bf4b500d2fe8f552735a28721f705 fpsr=00000000
-fmov s7, w15 b87fb552d02120cc96fce910c815b7b5 022499566a367eda49b0c2e5ab476577 000000000000000000000000ab476577 35a6a7f8600f343f49b0c2e5ab476577 fpsr=00000000
-fmov d7, x15 35954eb164b81a015d181eb0d13422c0 fefa2b0bfdbeddb488c900901dc5368c 000000000000000088c900901dc5368c ba6d23fbddcfb6e488c900901dc5368c fpsr=00000000
-fmov v7.d[1], x15 c38dbdaccabb5bcc988bec41d1f55876 c34a8a359bcdfb7cf3d1cf04bdfd4aa3 f3d1cf04bdfd4aa3988bec41d1f55876 76df5c23d344e727f3d1cf04bdfd4aa3 fpsr=00000000
-fmov w15, s7 40c9e0a4e28cc38e27b63222a6b73935 2f76953322c0b8926a280fa06b4f801c 40c9e0a4e28cc38e27b63222a6b73935 8da998f88c8b32a600000000a6b73935 fpsr=00000000
-fmov x15, d7 23de2e6573f9f357cd2f9fc5071aba58 c8746293ddf96221a55f780d618fa50b 23de2e6573f9f357cd2f9fc5071aba58 8a8cc509a7178875cd2f9fc5071aba58 fpsr=00000000
-fmov x15, v7.d[1] 313cbec68670df4e1ab8e17b2178e568 bafa353551a2546746b48a7dd8000fc0 313cbec68670df4e1ab8e17b2178e568 23de85e7f3ba676c313cbec68670df4e fpsr=00000000
-fmov d22, #0.125 9a985ec5f0031343f3185309c7b360a0 16da21aeefac01e48b55d9bb9a9e8466 00000000000000003fc0000000000000 16da21aeefac01e48b55d9bb9a9e8466 fpsr=00000000
-fmov d22, #-4.0 e2e823f1fc15de5d0fe0ad1832a0f513 0a452b2c674cbddfcbf508515b068b9e 0000000000000000c010000000000000 0a452b2c674cbddfcbf508515b068b9e fpsr=00000000
-fmov d22, #1.0 eb8aeda98a0320fe506fd007449d8620 759b310e98e167b9e8f5f99ff99706c8 00000000000000003ff0000000000000 759b310e98e167b9e8f5f99ff99706c8 fpsr=00000000
-fmov s22, #0.125 94e09c4d7a2fb98594259c37dc0df227 393d14b564cbe1d0c0b48a0655b1d345 0000000000000000000000003e000000 393d14b564cbe1d0c0b48a0655b1d345 fpsr=00000000
-fmov s22, #-4.0 bc4a103eacf98853bc63f107d94d1889 348ab47fa96b098734939ce54eb5d374 000000000000000000000000c0800000 348ab47fa96b098734939ce54eb5d374 fpsr=00000000
-fmov s22, #-1.0 442729db00c06ec7a888afd71cbfd9a5 48e3f1cf4820c03b24f10f9cc602e6b6 000000000000000000000000bf800000 48e3f1cf4820c03b24f10f9cc602e6b6 fpsr=00000000
-fmul v2.2d, v11.2d, v29.d[0] 0cd7c78555e44c4138f5b60885c215db 53a7ab02214be64e702ec38c9cf9ec6a 2e1c9d0c8757ad8f43446bb26e18386e 56fe35123930c0837383a1c149debce4 53a7ab02214be64e702ec38c9cf9ec6a 2e1c9d0c8757ad8f43446bb26e18386e fpsr=00000000
-fmul v2.2d, v11.2d, v29.d[1] bafd469c03bb81a72d0fa3c734a93060 5e28e61e7d9809fed89f25ffb69a16f0 dc31117d86c46bc9c3241e0a49fd7e17 fa6a8fb83d5e1b6974e09d3638780fcb 5e28e61e7d9809fed89f25ffb69a16f0 dc31117d86c46bc9c3241e0a49fd7e17 fpsr=00000000
-fmul v2.4s, v11.4s, v29.s[0] 033786b7c84ab17d3be2256e10956ff4 026a179172ccfc9a5caddec3a1b08243 7c4dbf374346e632cf6e8a894c18cbde 0f0bb86a7f74b273694f8d74ae52b3d0 026a179172ccfc9a5caddec3a1b08243 7c4dbf374346e632cf6e8a894c18cbde fpsr=00000000
-fmul v2.4s, v11.4s, v29.s[3] f6d81f33742433f2cc7dd6bb9c2cca19 53ca44aebd31b5254262bdc16b771596 b0e63d866320c355ed98b4a9e8d6e4c1 c535ea512e9fd374b3cbecf9dcde38c6 53ca44aebd31b5254262bdc16b771596 b0e63d866320c355ed98b4a9e8d6e4c1 fpsr=00000000
-fmul v2.2s, v11.2s, v29.s[0] eb0e45f4f7eae27ec0f14ecb50a5fc04 84562c36ddb9ea8ea8c8d0e79a950eb5 23c025e6d5d2e99c2ac801d7a6e270f6 00000000000000001031a1080203d8c1 84562c36ddb9ea8ea8c8d0e79a950eb5 23c025e6d5d2e99c2ac801d7a6e270f6 fpsr=00000000
-fmul v2.2s, v11.2s, v29.s[3] 95de8b5fc46113474bc49f812043d857 4912638e4626edfac3622c1b224d3e43 87e109bc0d20ad2cba8283f87c7f421f 00000000000000000bc6d15d80000000 4912638e4626edfac3622c1b224d3e43 87e109bc0d20ad2cba8283f87c7f421f fpsr=00000000
-fmul d2, d11, d29 a94b87d74f4b1970a17adfc3fe4a32b8 56017d1a6a3e158cc6b5e33ff7e57be5 914b7f6c80ce6328d14c4ff05df12fe2 000000000000000058135d856775f84e 56017d1a6a3e158cc6b5e33ff7e57be5 914b7f6c80ce6328d14c4ff05df12fe2 fpsr=00000000
-fmul s2, s11, s29 db5accc20d6d491ef5972073e0fedfcb 5e270e3ebfc4b369e7450a380da0993e f502195aa1a15db4a2a879a23d7c0ae2 0000000000000000000000000b9e1dad 5e270e3ebfc4b369e7450a380da0993e f502195aa1a15db4a2a879a23d7c0ae2 fpsr=00000000
-fmul v2.2d, v11.2d, v29.2d de0fee83708cf6737d9e7877b9a3b333 168aaa5db77c1eb35895b6ea59c26bf2 660b6deae45bf2f5621a15f41064a8c4 3ca6db571e2181167ac1b38410938f04 168aaa5db77c1eb35895b6ea59c26bf2 660b6deae45bf2f5621a15f41064a8c4 fpsr=00000000
-fmul v2.4s, v11.4s, v29.4s 676d807dee6a75966a13f9b17d7d8194 312ce5ddc92aa7904e2af939ce90c5a5 996a0d80bdc2740e452737c8cbeddc2b 8b1e133a4781a05853df5bab5b06837c 312ce5ddc92aa7904e2af939ce90c5a5 996a0d80bdc2740e452737c8cbeddc2b fpsr=00000000
-fmul v2.2s, v11.2s, v29.2s 2a781815facd19a8f37bb80620d01d92 651153206692a424fc88e808604c7cfc 42228e7fa19937237e53f304605c7bbb 0000000000000000ff8000007f800000 651153206692a424fc88e808604c7cfc 42228e7fa19937237e53f304605c7bbb fpsr=00000000
-fcvtn v22.2s, v23.2d db3648af097836cf4a5aca5a97e15cd2 643e888b037969929732973d033b649a 00000000000000007f80000080000000 643e888b037969929732973d033b649a fpsr=00000000
-fcvtn2 v22.4s, v23.2d bc4550d3fa5c74eac2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc 7f8000007f800000c2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc fpsr=00000000
-scvtf s7, w15 c5af844c56a6d2d3c616893fedf747e7 0f8bd808d4a0b2d247bb0dec2ea57f37 0000000000000000000000004e3a95fd 2cb55931f3d6b9c847bb0dec2ea57f37 fpsr=00000000
-scvtf d7, w15 d5d5c579fcb62eea358c328ece4911a6 957f97690fcf998c647b85644dc3143d 000000000000000041d370c50f400000 a6368e1cc3188fca647b85644dc3143d fpsr=00000000
-scvtf s7, x15 ce16f2bacbea6990f0908c45fcf43e06 bb263bb7ac3dd62d8563a61df253853d 000000000000000000000000def538b4 2f9b99a465c8ac618563a61df253853d fpsr=00000000
-scvtf d7, x15 8ed3ed6fa5a46224d78477c55858ae69 60e0a4508b474b138ad25076fcb5b098 0000000000000000c3dd4b6be240d294 a9435828b945f0ef8ad25076fcb5b098 fpsr=00000000
-ucvtf s7, w15 f76b95fa6844fb06cbc7d36dc1d5402f 650eb2968b4fd6a0532863cf4c4877ad 0000000000000000000000004e9890ef f28eac089ff03bd3532863cf4c4877ad fpsr=00000000
-ucvtf d7, w15 e73ec9b8f5291397a9ba7f9e19ccd6b6 aa0f44e98eb45934c0c5bf89c26cb8dc 000000000000000041e84d971b800000 ebdd75a5f6276c6ec0c5bf89c26cb8dc fpsr=00000000
-randV128: 512 calls, 530 iters
-ucvtf s7, x15 3fad6a0b2cb3893654bc5db73e9c4e61 0f443ca873d6b22db10a44033e825486 0000000000000000000000005f310a44 7490935e9f4d651fb10a44033e825486 fpsr=00000000
-ucvtf d7, x15 df175852ed423e44ab2d4b1812a6898d 740c78331916c2ee0656d19da0e92b0a 000000000000000043995b467683a4ac 6d05e6937bbf04460656d19da0e92b0a fpsr=00000000
-abs d22, d23 a7dc73ed183713208e6e2a227349679c b9c7d9eb61d469d49e0a48b8c8011cc8 000000000000000061f5b74737fee338 b9c7d9eb61d469d49e0a48b8c8011cc8 fpsr=00000000
-neg d22, d23 765d9b3d8cf2e62adcdeda3442e5c8ed bed6402f2b6e86415b8587b3952b0921 0000000000000000a47a784c6ad4f6df bed6402f2b6e86415b8587b3952b0921 fpsr=00000000
-abs v8.2d, v7.2d2ef9b0a22bd197c376de3baf5fdb8ce1 2ef9b0a22bd197c376de3baf5fdb8ce1 fpsr=00000000
-abs v8.4s, v7.4se7f00989302dba7246518421715669c6 180ff677302dba7246518421715669c6 fpsr=00000000
-abs v8.2s, v7.2sad11927ad336084a3ccd2df1aa8a93d7 00000000000000003ccd2df155756c29 fpsr=00000000
-abs v8.8h, v7.8hdea946e0b179bef5361cb20c2785c541 215746e04e87410b361c4df427853abf fpsr=00000000
-abs v8.4h, v7.4hd50420276581181f0f0b8f5d0353bc2f 00000000000000000f0b70a3035343d1 fpsr=00000000
-abs v8.16b, v7.16bed6e1ebb8cda5175a26641cf5aff34ce 136e1e45742651755e6641315a013432 fpsr=00000000
-abs v8.8b, v7.8b84323c09c110a7a3ccf943504995e94a 000000000000000034074350496b174a fpsr=00000000
-neg v8.2d, v7.2df49e747ba1b053546a8f11cbec2196ce 0b618b845e4facac9570ee3413de6932 fpsr=00000000
-neg v8.4s, v7.4s9bfcc47ec746943556f6272c5eb0f887 64033b8238b96bcba909d8d4a14f0779 fpsr=00000000
-neg v8.2s, v7.2sd399277fd05ca4f26ef8025fbb4dcba1 00000000000000009107fda144b2345f fpsr=00000000
-neg v8.8h, v7.8hfac199e95780c0368c621d512005ca47 053f6617a8803fca739ee2afdffb35b9 fpsr=00000000
-neg v8.4h, v7.4h6ac01727f93e24ad8d00f4eca9e2b2a5 000000000000000073000b14561e4d5b fpsr=00000000
-neg v8.16b, v7.16b81e19ba751200b054e9e031d71f33fe9 7f1f6559afe0f5fbb262fde38f0dc117 fpsr=00000000
-neg v8.8b, v7.8b997223d4fcb4b3e7a908c6d194412d3c 000000000000000057f83a2f6cbfd3c4 fpsr=00000000
-add d21, d22, d23 0fbdaa1a958555027b09baf22fda37cd de05200cbf652c8e4966c11a56eab69e 3f0f2ce5b8203000a06e5a6e5dc91ac6 0000000000000000e9d51b88b4b3d164 de05200cbf652c8e4966c11a56eab69e 3f0f2ce5b8203000a06e5a6e5dc91ac6 fpsr=00000000
-sub d21, d22, d23 3ef813ba0fe17c5753958e24e4db5aa2 c4276f9d7a2066089aed1b36751530dd a5d2c97f7788bae1eca9a838c108ae44 0000000000000000ae4372fdb40c8299 c4276f9d7a2066089aed1b36751530dd a5d2c97f7788bae1eca9a838c108ae44 fpsr=00000000
-add v9.2d, v7.2d, v8.2d a936258b9666b4d4f37549976fb022ff c32cf63309e402406e9f5a58ac1a54d1 6c631bbea04ab7146214a3f01bca77d0 fpsr=00000000
-add v9.4s, v7.4s, v8.4s 19fee7710650f247e80f3f1bf2b5b476 ec6d05a4b6a1a4cd9e88325743eb11d5 066bed15bcf297148697717236a0c64b fpsr=00000000
-add v9.2s, v7.2s, v8.2s eb961e83edc02ffa57cb79e901fcadd7 ef23560adb3157cc50072abaf61c5a46 0000000000000000a7d2a4a3f819081d fpsr=00000000
-add v9.8h, v7.8h, v8.8h 270ecc3cebbd43a2f727286eebfe18c9 727e8a02b5bb9511dbbd140db245d8e8 998c563ea178d8b3d2e43c7b9e43f1b1 fpsr=00000000
-add v9.4h, v7.4h, v8.4h b2d6d57a7db0e9535f056177dd93e04f fd0f238763c9b9d176aaa13e475e17e0 0000000000000000d5af02b524f1f82f fpsr=00000000
-add v9.16b, v7.16b, v8.16b 52bffb790361bc8206a61431e6f4cfcd f4c785f8e443fea0362f659862c280b3 46868071e7a4ba223cd579c948b64f80 fpsr=00000000
-add v9.8b, v7.8b, v8.8b b0f9e0d5b9fa370241a91527f6b99009 a0f5f10f15717d72120cd2c993275e44 000000000000000053b5e7f089e0ee4d fpsr=00000000
-sub v9.2d, v7.2d, v8.2d 5015078bc002b309470f1546d9dbad27 264b8be9b6fd329ce1613adc48a6dcd9 29c97ba20905806d65adda6a9134d04e fpsr=00000000
-sub v9.4s, v7.4s, v8.4s 9a04d2f816626c2c2f38a8db40b290ab 8dd9540466eef7d359b0d13fcfb80416 0c2b7ef4af737459d587d79c70fa8c95 fpsr=00000000
-sub v9.2s, v7.2s, v8.2s d31583d898627c5eefe64192b7f7857a bc0f303ba1ad862b11d8a7bd5735c0ff 0000000000000000de0d99d560c1c47b fpsr=00000000
-sub v9.8h, v7.8h, v8.8h 23fa3e4706acddf45d393078afc3b5d8 78bee0cbc8037a197f1bb183ee56dcf9 ab3c5d7c3ea963dbde1e7ef5c16dd8df fpsr=00000000
-sub v9.4h, v7.4h, v8.4h 90c305c2fe476aa231b0aaf9758d2b6b 6917085019174d71f918c11e83b301c8 00000000000000003898e9dbf1da29a3 fpsr=00000000
-sub v9.16b, v7.16b, v8.16b 15a929c7b1735a67b7d0887be445bb91 5f3646169d10a4a4a96e8ad5ed65b981 b673e3b11463b6c30e62fea6f7e00210 fpsr=00000000
-sub v9.8b, v7.8b, v8.8b e266a78d90ffdc91cea49ae5c06573d8 725aaa117e7599eb792f879592071e89 0000000000000000557513502e5e554f fpsr=00000000
-addhn v9.2s, v7.2d, v8.2d 189dc35e9404ece236546909a6ca7482 8737670045ac078c562d87a75d3333b4 00000000000000009fd52a5e8c81f0b1 fpsr=00000000
-addhn2 v9.4s, v7.2d, v8.2d 1c7493622cfa2597b6855d5cd44e174a 868b2e22d97fdd69760648ac6426460c a2ffc1852c8ba609302a67122627dc71 fpsr=00000000
-addhn v9.4h, v7.4s, v8.4s 216a7d91960bd145f0fdfb1c6ec3212c 2906701b0eb55d7aa1e722b770cb3d54 00000000000000004a70a4c192e5df8e fpsr=00000000
-addhn2 v9.8h, v7.4s, v8.4s 58f31949403befabe5870936cd45f720 96584f08a2f98312aff067d5f03b44cf ef4be3359577bd81d8d7987a5aa2c601 fpsr=00000000
-addhn v9.8b, v7.8h, v8.8h 29fec9e82973b95bac8519f59f2d04ab d592cd65355229e856a34b7132ed6522 0000000000000000ff975ee30365d269 fpsr=00000000
-addhn2 v9.16b, v7.8h, v8.8h cb24ce0e442a090e2de0df5a65ba8b51 89dc3ea5a31f12c364df0e25357e07d6 550ce71b92ed9b936a3eec76b56ecb74 fpsr=00000000
-subhn v9.2s, v7.2d, v8.2d 3edf14402e48bffaabe616bb98dc80c1 ccbe78e080dd716773220ebf7179adb2 000000000000000072209b5f38c407fc fpsr=00000000
-subhn2 v9.4s, v7.2d, v8.2d d6f4419831d4c3802458c320b8e9ef36 2a1fe48bf7d8b25706c5dff7abfe7295 acd45d0c1d92e3295bab8685a4c94b2d fpsr=00000000
-subhn v9.4h, v7.4s, v8.4s 19f3d7116d5971d5d234977794db61d6 cbafa6c1c5b8d1e7f3e9d3da51267dc3 00000000000000004e44a7a0de4a43b4 fpsr=00000000
-subhn2 v9.8h, v7.4s, v8.4s 6ecc3a09dfbd048cc8dc260bdc0b4323 b57fbffe8986a7cbf20e1dd4b168dbe1 b94c5636d6ce2aa2b651fc046084577a fpsr=00000000
-subhn v9.8b, v7.8h, v8.8h 1acfac3d674a969cff10e3891c30dd04 cfff1221c2a9f0189914d0b1f99e76f3 00000000000000004a9aa4a665122266 fpsr=00000000
-subhn2 v9.16b, v7.8h, v8.8h 45af4ec7c2a821574df11effc5645bbb de016364cdeb46445e3dde9f39ff175e 67ebf4dbef408b44adb462d8dde2c3fe fpsr=00000000
-raddhn v9.2s, v7.2d, v8.2d f57a25258fdf807367ff0cd7231ec7ef 8ab45265eb7423219729192a5f256ae7 0000000000000000802e778bff282602 fpsr=00000000
-raddhn2 v9.4s, v7.2d, v8.2d 10a112344c596d04e61bbedf67380ca3 59a8632038cce2e47cd7343d3907fab1 6a49755562f2f31d7557cde51027645d fpsr=00000000
-raddhn v9.4h, v7.4s, v8.4s 5df6d73059dd837e3e8527449ee9f43b b1cff9f1b4ddbe2322a9c22776ff3042 00000000000000000fc70ebb612f15e9 fpsr=00000000
-raddhn2 v9.8h, v7.4s, v8.4s 83a818b6f3943cb7c8dd1991b6cb297d d97955953deed0d281603593a4c5577d 5d2131834a3d5b9142bf4f0fec980e3b fpsr=00000000
-raddhn v9.8b, v7.8h, v8.8h f7579b2891a813446e1bdf8d327099a8 fcd880ce0be4bb73cf8ab30ab9b9dc22 0000000000000000f41c9ecf3e93ec76 fpsr=00000000
-raddhn2 v9.16b, v7.8h, v8.8h 1378cc285014632fa05bf3836f7b0267 3ca9b2f8c2eaf1274870fd3a6577943d 507f1354e9f1d59709648309bc276589 fpsr=00000000
-rsubhn v9.2s, v7.2d, v8.2d 124ecb70f79979a7ae01844088bd7bbe 1614be74a19641dae470df8abcc9c0b3 0000000000000000fc3a0cfcc990a4b6 fpsr=00000000
-rsubhn2 v9.4s, v7.2d, v8.2d baa85b3de501ef210e4d83f18c6ed012 f209069ea7d3e520baedeb496f09ca07 c89f549f535f98a864c5ec2b482151d1 fpsr=00000000
-rsubhn v9.4h, v7.4s, v8.4s b4b81f2b5975417117dfc4246b28aa27 15dacc33b1e8f8eec0a594220beffe1d 00000000000000009edda78c573a5f39 fpsr=00000000
-rsubhn2 v9.8h, v7.4s, v8.4s a73535507f7e7497cdba2d21fe93853b 98666b7ee7341f88fecd97fa1709cf0b 0ecf984aceede78add3bb51ccef7f987 fpsr=00000000
-rsubhn v9.8b, v7.8h, v8.8h ae2d4071b09e34d197ade8b4986d6b05 ebd55f51b7352d94362d6f4fc8df6c3a 0000000000000000c2e1f9076279d0ff fpsr=00000000
-rsubhn2 v9.16b, v7.8h, v8.8h 1130d272c0b0f3b1b55dd7a60757997f 5136e60ea8b68eb60aff985d1d21b4da c0ec1865aa3feae534966a0ea86c3d83 fpsr=00000000
-addp d22, v23.2d 9511ad90107c4aa99c0bee255989da0e 30796011b79f7a8390a6a371c6291371 0000000000000000c12003837dc88df4 30796011b79f7a8390a6a371c6291371 fpsr=00000000
-addp v9.2d, v7.2d, v8.2d d0f01218c3380ef0bee102374fafd4e3 d0d6b3fdf02b399c4f77f7dceacd49be 204eabdadaf8835a8fd1145012e7e3d3 fpsr=00000000
-addp v9.4s, v7.4s, v8.4s 56491d3d8b2a43506ad00abc28cb1f74 b2aa237461d97084eb06887153eff01a 148393f83ef6788be173608d939b2a30 fpsr=00000000
-addp v9.2s, v7.2s, v8.2s c89783ffad7ef35a4cf4eb6ba0f602c9 99375b70cb57d76663606f6b895df1dc 0000000000000000ecbe6147edeaee34 fpsr=00000000
-addp v9.8h, v7.8h, v8.8h 0e492839a79cda20f92eb913e40864e6 0a0edcee4d2cc878ef855eb65c10d628 e6fc15a44e3b3238368281bcb24148ee fpsr=00000000
-addp v9.4h, v7.4h, v8.4h ee30cd29d94c9218e8bf66df043a1230 6d1f094ae6417d4ca4d5e89f7a600a82 00000000000000008d7484e24f9e166a fpsr=00000000
-addp v9.16b, v7.16b, v8.16b 0f7c166980b896167145c55bed24b56c 08bc254274de12d879127ed27105d7cf c46752ea8b5076a68b7f38acb6201121 fpsr=00000000
-addp v9.8b, v7.8b, v8.8b f6be84f8bb673f4fc8c387756fbfd9bd 029353f1b5ac7f6f455b745cb01a6853 0000000000000000a0d0cabb8bfc2e96 fpsr=00000000
-addv s22, v23.4s 0be77b318842c856059940783863e7a8 60b794d448b4a0c8be32fda98514c6b3 000000000000000000000000ecb3f9f8 60b794d448b4a0c8be32fda98514c6b3 fpsr=00000000
-addv h22, v23.8h 0a97cbc7ac5e30f57b7629851fcfdef3 419ca01490f7f11f910033957a94279b 0000000000000000000000000000ca8a 419ca01490f7f11f910033957a94279b fpsr=00000000
-addv h22, v23.4h a8fb004a32b8ef7bf67abbd38dacaf39 7bcc8918719010b51f8d0a9a2b9cdad6 00000000000000000000000000003099 7bcc8918719010b51f8d0a9a2b9cdad6 fpsr=00000000
-addv b22, v23.16b c773fa18fab0e4465406d6c1605a3bd8 eca72f41cddddee9493a63177b8ec0c3 000000000000000000000000000000fd eca72f41cddddee9493a63177b8ec0c3 fpsr=00000000
-addv b22, v23.8b 455d9993e4a5f1b876795aaf7a3a6332 768d72ee82413c1cef651c6c49c9b9c3 0000000000000000000000000000006a 768d72ee82413c1cef651c6c49c9b9c3 fpsr=00000000
-and v9.16b, v7.16b, v8.16b 031cbc1bd0f7f4313c3427feb9ab05a7 f7df3280711908adf17116fa75aea535 031c300050110021303006fa31aa0525 fpsr=00000000
-and v9.8b, v7.8b, v8.8b 1a8f772c44efeda7ba0881e4f45d0ce7 e10d450f9d06ce0f86961d0dfe0e0295 000000000000000082000104f40c0085 fpsr=00000000
-bic v9.16b, v7.16b, v8.16b 621745bf1e53a253c283fdabe8787949 f376b669ae2ce35a2a57a09a50746818 0001419610530001c0805d21a8081141 fpsr=00000000
-bic v9.8b, v7.8b, v8.8b 6146a9d07daa6c6a88a64c3f65f3d5f0 54caa9aa633342e0b5d4f4aedaf80203 0000000000000000082208112503d5f0 fpsr=00000000
-orr v9.16b, v7.16b, v8.16b 7d0a04bc5edd878025d002ec19278d62 091a1f4f5923c556de8f49b6eb14daf9 7d1a1fff5fffc7d6ffdf4bfefb37dffb fpsr=00000000
-orr v9.8b, v7.8b, v8.8b fdb69b3e9f350d8a8dc2926092cde983 fad6fc35116526d23a68b37db09eda00 0000000000000000bfeab37db2dffb83 fpsr=00000000
-orn v9.16b, v7.16b, v8.16b 07f98f74015af8db989c4ca73ffe1597 edcf0197e7c200c7409e243038d0ce7b 17f9ff7c197ffffbbffddfefffff3597 fpsr=00000000
-orn v9.8b, v7.8b, v8.8b a2e4e3d92054232afde0652d6f311b42 8836d1131b62cd0b48d36e5b73435f30 0000000000000000ffecf5adefbdbbcf fpsr=00000000
-orr v22.8h, #0x5A, LSL #0 b5e8784c7c8c4889516eeebe4f40e68b 539af0a5cbcde8d1860844ed2dee1843 b5fa785e7cde48db517eeefe4f5ae6db 539af0a5cbcde8d1860844ed2dee1843 fpsr=00000000
-orr v22.8h, #0xA5, LSL #8 b2edbeaaf5ec8bae129c392f172a6438 1b5c9af6cf5b3c778baf84856af42855 b7edbfaaf5ecafaeb79cbd2fb72ae538 1b5c9af6cf5b3c778baf84856af42855 fpsr=00000000
-orr v22.4h, #0x5A, LSL #0 f0c7891470a9c6d97711cd0105a75eff db89c02a0d5fff7bec35055605a42bda 0000000000000000775bcd5b05ff5eff db89c02a0d5fff7bec35055605a42bda fpsr=00000000
-orr v22.4h, #0xA5, LSL #8 4dd3b8ebcc24d76b5f2e8993f914b241 738244a36537113d88fba7bfdd5d0131 0000000000000000ff2ead93fd14b741 738244a36537113d88fba7bfdd5d0131 fpsr=00000000
-orr v22.4s, #0x5A, LSL #0 a9732d8eebbc9fc3ac524f46d3d3415d c3a505c0b746521e41604a20d37f8abb a9732ddeebbc9fdbac524f5ed3d3415f c3a505c0b746521e41604a20d37f8abb fpsr=00000000
-randV128: 768 calls, 793 iters
-orr v22.4s, #0x6B, LSL #8 ab54e2e2e2e9a17df5c4cddac86ba5d7 df49d6a4ee899c7ee449c250d31cbfc2 ab54ebe2e2e9eb7df5c4efdac86befd7 df49d6a4ee899c7ee449c250d31cbfc2 fpsr=00000000
-orr v22.4s, #0x49, LSL #16 0aefbd68c882e0ba8688124d9a8034e6 4f3e6b0b450ee14a3f6391173f4b1584 0aefbd68c8cbe0ba86c9124d9ac934e6 4f3e6b0b450ee14a3f6391173f4b1584 fpsr=00000000
-orr v22.4s, #0x3D, LSL #24 d015d40d6e016dac0dd5facfa21a36f1 84629830272617d94573bcb41f7f9ba4 fd15d40d7f016dac3dd5facfbf1a36f1 84629830272617d94573bcb41f7f9ba4 fpsr=00000000
-orr v22.2s, #0x5A, LSL #0 4030f30c48c120052fffdbd7daec0268 a42d5ff531c8df470f895737f09f7c94 00000000000000002fffdbdfdaec027a a42d5ff531c8df470f895737f09f7c94 fpsr=00000000
-orr v22.2s, #0x6B, LSL #8 80efa667b5aedab485401690c81e5949 4b33b2ee05b02563c54f4243ae396147 000000000000000085407f90c81e7b49 4b33b2ee05b02563c54f4243ae396147 fpsr=00000000
-orr v22.2s, #0x49, LSL #16 70b1ce7f93297a1aeff889594c121bf4 5ad5737c833dcb8d47245f373bad281c 0000000000000000eff989594c5b1bf4 5ad5737c833dcb8d47245f373bad281c fpsr=00000000
-orr v22.2s, #0x3D, LSL #24 f0d64bb3c491e2964c871592462727ca b17280fe8bd0af2574688c737559b274 00000000000000007d8715927f2727ca b17280fe8bd0af2574688c737559b274 fpsr=00000000
-bic v22.8h, #0x5A, LSL #0 e0bffd642647f0887e4e9a9b96be5e2b 306bbad4fdc8b28c2e7caa583d9fdfad e0a5fd242605f0807e049a8196a45e21 306bbad4fdc8b28c2e7caa583d9fdfad fpsr=00000000
-bic v22.8h, #0xA5, LSL #8 20cbc3f09aaa865164adf8d51b36a175 b61e015fb...
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