|
From: <sv...@va...> - 2014-05-06 09:30:43
|
Author: sewardj
Date: Tue May 6 09:30:29 2014
New Revision: 13936
Log:
Big reorganisation:
* add lane type descriptors, to be used by the random data
generators -- as-yet unused
* move existing tests into new groupings, and rename some of
them to be more consistent with the new notation.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Tue May 6 09:30:29 2014
@@ -17,8 +17,11 @@
#define True ((Bool)1)
-#define ITERS 10
+#define ITERS 1
+typedef
+ enum { TySF=1234, TyDF, TyB, TyH, TyS, TyD, TyNONE }
+ LaneTy;
union _V128 {
UChar u8[16];
@@ -37,7 +40,7 @@
return (seed >> 17) & 0xFF;
}
-static ULong randULong ( void )
+static ULong randULong ( LaneTy ty )
{
Int i;
ULong r = 0;
@@ -50,7 +53,7 @@
/* Generates a random V128. Ensures that that it contains normalised
FP numbers when viewed as either F32x4 or F64x2, so that it is
reasonable to use in FP test cases. */
-static void randV128 ( V128* v )
+static void randV128 ( /*OUT*/V128* v, LaneTy ty )
{
static UInt nCalls = 0, nIters = 0;
Int i;
@@ -86,6 +89,188 @@
}
+/* ---------------------------------------------------------------- */
+/* -- Test functions -- */
+/* ---------------------------------------------------------------- */
+
+/* Note this also sets the destination register to a known value (0x55..55)
+ since it can sometimes be an input to the instruction too. */
+#define GEN_UNARY_TEST(INSN,SUFFIXD,SUFFIXN) \
+ __attribute__((noinline)) \
+ static void test_##INSN##_##SUFFIXD##_##SUFFIXN ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[2]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ __asm__ __volatile__( \
+ "ldr q7, [%0, #0] ; " \
+ "ldr q8, [%0, #16] ; " \
+ #INSN " v8." #SUFFIXD ", v7." #SUFFIXN " ; " \
+ "str q8, [%0, #16] " \
+ : : "r"(&block[0]) : "memory", "v7", "v8" \
+ ); \
+ printf(#INSN " v8." #SUFFIXD ", v7." #SUFFIXN); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf("\n"); \
+ } \
+ }
+
+
+/* Note this also sets the destination register to a known value (0x55..55)
+ since it can sometimes be an input to the instruction too. */
+#define GEN_BINARY_TEST(INSN,SUFFIXD,SUFFIXN,SUFFIXM) \
+ __attribute__((noinline)) \
+ static void test_##INSN##_##SUFFIXD##_##SUFFIXN##_##SUFFIXM ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[3]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ __asm__ __volatile__( \
+ "ldr q7, [%0, #0] ; " \
+ "ldr q8, [%0, #16] ; " \
+ "ldr q9, [%0, #32] ; " \
+ #INSN " v9." #SUFFIXD ", v7." #SUFFIXN ", v8." #SUFFIXM " ; " \
+ "str q9, [%0, #32] " \
+ : : "r"(&block[0]) : "memory", "v7", "v8", "v9" \
+ ); \
+ printf(#INSN " v9." #SUFFIXD \
+ ", v7." #SUFFIXN ", v8." #SUFFIXM " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf("\n"); \
+ } \
+ }
+
+
+/* Note this also sets the destination register to a known value (0x55..55)
+ since it can sometimes be an input to the instruction too. */
+#define GEN_SHIFT_TEST(INSN,SUFFIXD,SUFFIXN,AMOUNT) \
+ __attribute__((noinline)) \
+ static void test_##INSN##_##SUFFIXD##_##SUFFIXN##_##AMOUNT ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[2]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ __asm__ __volatile__( \
+ "ldr q7, [%0, #0] ; " \
+ "ldr q8, [%0, #16] ; " \
+ #INSN " v8." #SUFFIXD ", v7." #SUFFIXN ", #" #AMOUNT " ; " \
+ "str q8, [%0, #16] " \
+ : : "r"(&block[0]) : "memory", "v7", "v8" \
+ ); \
+ printf(#INSN " v8." #SUFFIXD ", v7." #SUFFIXN ", #" #AMOUNT " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf("\n"); \
+ } \
+ }
+
+
+/* Generate a test that involves one integer reg and one vector reg,
+ with no bias as towards which is input or output. */
+#define GEN_ONEINT_ONEVEC_TEST(TESTNAME,INSN,INTREGNO,VECREGNO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ __asm__ __volatile__( \
+ "ldr q"#VECREGNO", [%0, #0] ; " \
+ "ldr x"#INTREGNO", [%0, #16] ; " \
+ INSN " ; " \
+ "str q"#VECREGNO", [%0, #32] ; " \
+ "str x"#INTREGNO", [%0, #48] ; " \
+ : : "r"(&block[0]) : "memory", "v"#VECREGNO, "x"#INTREGNO \
+ ); \
+ printf(INSN " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf("\n"); \
+ } \
+ }
+
+
+/* Generate a test that involves two vector regs,
+ with no bias as towards which is input or output. */
+#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ __asm__ __volatile__( \
+ "ldr q"#VECREG1NO", [%0, #0] ; " \
+ "ldr q"#VECREG2NO", [%0, #16] ; " \
+ INSN " ; " \
+ "str q"#VECREG1NO", [%0, #32] ; " \
+ "str q"#VECREG2NO", [%0, #48] ; " \
+ : : "r"(&block[0]) : "memory", "v"#VECREG1NO, "v"#VECREG2NO \
+ ); \
+ printf(INSN " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf("\n"); \
+ } \
+ }
+
+
+/* Generate a test that involves three vector regs,
+ with no bias as towards which is input or output. It's also OK
+ to use v16, v17, v18 as scratch. */
+#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[6]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ randV128(&block[4], ty); \
+ randV128(&block[5], ty); \
+ __asm__ __volatile__( \
+ "ldr q"#VECREG1NO", [%0, #0] ; " \
+ "ldr q"#VECREG2NO", [%0, #16] ; " \
+ "ldr q"#VECREG3NO", [%0, #32] ; " \
+ INSN " ; " \
+ "str q"#VECREG1NO", [%0, #48] ; " \
+ "str q"#VECREG2NO", [%0, #64] ; " \
+ "str q"#VECREG3NO", [%0, #80] ; " \
+ : : "r"(&block[0]) \
+ : "memory", "v"#VECREG1NO, "v"#VECREG2NO, "v"#VECREG3NO, \
+ "v16", "v17", "v18" \
+ ); \
+ printf(INSN " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf("\n"); \
+ } \
+ }
+
+
void test_UMINV ( void )
{
int i;
@@ -95,8 +280,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyS);
+ randV128(&block[1], TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv s8, v7.4s ; "
@@ -112,8 +297,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv h8, v7.8h ; "
@@ -129,8 +314,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv h8, v7.4h ; "
@@ -146,8 +331,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv b8, v7.16b ; "
@@ -163,8 +348,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv b8, v7.8b ; "
@@ -188,8 +373,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyS);
+ randV128(&block[1], TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv s8, v7.4s ; "
@@ -205,8 +390,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv h8, v7.8h ; "
@@ -222,8 +407,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv h8, v7.4h ; "
@@ -239,8 +424,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv b8, v7.16b ; "
@@ -256,8 +441,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv b8, v7.8b ; "
@@ -279,7 +464,7 @@
/* -- D[0..1] -- */
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyD);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -292,7 +477,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyD);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -307,7 +492,7 @@
/* -- S[0..3] -- */
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -320,7 +505,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -333,7 +518,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -346,7 +531,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -361,7 +546,7 @@
/* -- H[0..7] -- */
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -374,7 +559,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -387,7 +572,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -400,7 +585,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -413,7 +598,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -426,7 +611,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -439,7 +624,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -452,7 +637,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -467,7 +652,7 @@
/* -- B[0,15] -- */
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -480,7 +665,7 @@
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].u64[0] = randULong();
+ block[1].u64[0] = randULong(TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -504,8 +689,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyS);
+ randV128(&block[1], TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv s8, v7.4s ; "
@@ -521,8 +706,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv h8, v7.8h ; "
@@ -538,8 +723,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv h8, v7.4h ; "
@@ -555,8 +740,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv b8, v7.16b ; "
@@ -572,8 +757,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv b8, v7.8b ; "
@@ -597,8 +782,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyS);
+ randV128(&block[1], TyS);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv s8, v7.4s ; "
@@ -614,8 +799,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv h8, v7.8h ; "
@@ -631,8 +816,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyH);
+ randV128(&block[1], TyH);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv h8, v7.4h ; "
@@ -648,8 +833,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv b8, v7.16b ; "
@@ -665,8 +850,8 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
- randV128(&block[0]);
- randV128(&block[1]);
+ randV128(&block[0], TyB);
+ randV128(&block[1], TyB);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv b8, v7.8b ; "
@@ -680,215 +865,143 @@
}
-/* Note this also sets the destination register to a known value (0x55..55)
- since it can sometimes be an input to the instruction too. */
-#define GEN_BINARY_TEST(INSN,SUFFIX) \
- __attribute__((noinline)) \
- static void test_##INSN##_##SUFFIX ( void ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[3]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0]); \
- randV128(&block[1]); \
- randV128(&block[2]); \
- __asm__ __volatile__( \
- "ldr q7, [%0, #0] ; " \
- "ldr q8, [%0, #16] ; " \
- "ldr q9, [%0, #32] ; " \
- #INSN " v9." #SUFFIX ", v7." #SUFFIX ", v8." #SUFFIX " ; " \
- "str q9, [%0, #32] " \
- : : "r"(&block[0]) : "memory", "v7", "v8", "v9" \
- ); \
- printf(#INSN " v9." #SUFFIX ", v7." #SUFFIX ", v8." #SUFFIX " "); \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf(" "); \
- showV128(&block[2]); printf("\n"); \
- } \
- }
-
-
-/* Note this also sets the destination register to a known value (0x55..55)
- since it can sometimes be an input to the instruction too. */
-#define GEN_SHIFT_TEST(INSN,SUFFIXD,SUFFIXN,AMOUNT) \
- __attribute__((noinline)) \
- static void test_##INSN##_##SUFFIXD##_##SUFFIXN##_##AMOUNT ( void ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[2]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0]); \
- randV128(&block[1]); \
- __asm__ __volatile__( \
- "ldr q7, [%0, #0] ; " \
- "ldr q8, [%0, #16] ; " \
- #INSN " v8." #SUFFIXD ", v7." #SUFFIXN ", #" #AMOUNT " ; " \
- "str q8, [%0, #16] " \
- : : "r"(&block[0]) : "memory", "v7", "v8" \
- ); \
- printf(#INSN " v8." #SUFFIXD ", v7." #SUFFIXN ", #" #AMOUNT " "); \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf("\n"); \
- } \
- }
-
-/* Note this also sets the destination register to a known value (0x55..55)
- since it can sometimes be an input to the instruction too. */
-#define GEN_UNARY_TEST(INSN,SUFFIXD,SUFFIXN) \
- __attribute__((noinline)) \
- static void test_##INSN##_##SUFFIXD##_##SUFFIXN ( void ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[2]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0]); \
- randV128(&block[1]); \
- __asm__ __volatile__( \
- "ldr q7, [%0, #0] ; " \
- "ldr q8, [%0, #16] ; " \
- #INSN " v8." #SUFFIXD ", v7." #SUFFIXN " ; " \
- "str q8, [%0, #16] " \
- : : "r"(&block[0]) : "memory", "v7", "v8" \
- ); \
- printf(#INSN " v8." #SUFFIXD ", v7." #SUFFIXN); \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf("\n"); \
- } \
- }
-
-GEN_BINARY_TEST(umax, 4s)
-GEN_BINARY_TEST(umax, 8h)
-GEN_BINARY_TEST(umax, 4h)
-GEN_BINARY_TEST(umax, 16b)
-GEN_BINARY_TEST(umax, 8b)
-
-GEN_BINARY_TEST(umin, 4s)
-GEN_BINARY_TEST(umin, 8h)
-GEN_BINARY_TEST(umin, 4h)
-GEN_BINARY_TEST(umin, 16b)
-GEN_BINARY_TEST(umin, 8b)
-
-GEN_BINARY_TEST(smax, 4s)
-GEN_BINARY_TEST(smax, 8h)
-GEN_BINARY_TEST(smax, 4h)
-GEN_BINARY_TEST(smax, 16b)
-GEN_BINARY_TEST(smax, 8b)
-
-GEN_BINARY_TEST(smin, 4s)
-GEN_BINARY_TEST(smin, 8h)
-GEN_BINARY_TEST(smin, 4h)
-GEN_BINARY_TEST(smin, 16b)
-GEN_BINARY_TEST(smin, 8b)
-
-GEN_BINARY_TEST(add, 2d)
-GEN_BINARY_TEST(add, 4s)
-GEN_BINARY_TEST(add, 2s)
-GEN_BINARY_TEST(add, 8h)
-GEN_BINARY_TEST(add, 4h)
-GEN_BINARY_TEST(add, 16b)
-GEN_BINARY_TEST(add, 8b)
-
-GEN_BINARY_TEST(sub, 2d)
-GEN_BINARY_TEST(sub, 4s)
-GEN_BINARY_TEST(sub, 2s)
-GEN_BINARY_TEST(sub, 8h)
-GEN_BINARY_TEST(sub, 4h)
-GEN_BINARY_TEST(sub, 16b)
-GEN_BINARY_TEST(sub, 8b)
-
-GEN_BINARY_TEST(mul, 4s)
-GEN_BINARY_TEST(mul, 2s)
-GEN_BINARY_TEST(mul, 8h)
-GEN_BINARY_TEST(mul, 4h)
-GEN_BINARY_TEST(mul, 16b)
-GEN_BINARY_TEST(mul, 8b)
-
-GEN_BINARY_TEST(mla, 4s)
-GEN_BINARY_TEST(mla, 2s)
-GEN_BINARY_TEST(mla, 8h)
-GEN_BINARY_TEST(mla, 4h)
-GEN_BINARY_TEST(mla, 16b)
-GEN_BINARY_TEST(mla, 8b)
-
-GEN_BINARY_TEST(mls, 4s)
-GEN_BINARY_TEST(mls, 2s)
-GEN_BINARY_TEST(mls, 8h)
-GEN_BINARY_TEST(mls, 4h)
-GEN_BINARY_TEST(mls, 16b)
-GEN_BINARY_TEST(mls, 8b)
-
-GEN_BINARY_TEST(and, 16b)
-GEN_BINARY_TEST(and, 8b)
-
-GEN_BINARY_TEST(bic, 16b)
-GEN_BINARY_TEST(bic, 8b)
-
-GEN_BINARY_TEST(orr, 16b)
-GEN_BINARY_TEST(orr, 8b)
-
-GEN_BINARY_TEST(orn, 16b)
-GEN_BINARY_TEST(orn, 8b)
-
-GEN_BINARY_TEST(eor, 16b)
-GEN_BINARY_TEST(eor, 8b)
-
-GEN_BINARY_TEST(bsl, 16b)
-GEN_BINARY_TEST(bsl, 8b)
-
-GEN_BINARY_TEST(bit, 16b)
-GEN_BINARY_TEST(bit, 8b)
-
-GEN_BINARY_TEST(bif, 16b)
-GEN_BINARY_TEST(bif, 8b)
-
-GEN_BINARY_TEST(cmeq, 2d)
-GEN_BINARY_TEST(cmeq, 4s)
-GEN_BINARY_TEST(cmeq, 2s)
-GEN_BINARY_TEST(cmeq, 8h)
-GEN_BINARY_TEST(cmeq, 4h)
-GEN_BINARY_TEST(cmeq, 16b)
-GEN_BINARY_TEST(cmeq, 8b)
-
-GEN_BINARY_TEST(cmtst, 2d)
-GEN_BINARY_TEST(cmtst, 4s)
-GEN_BINARY_TEST(cmtst, 2s)
-GEN_BINARY_TEST(cmtst, 8h)
-GEN_BINARY_TEST(cmtst, 4h)
-GEN_BINARY_TEST(cmtst, 16b)
-GEN_BINARY_TEST(cmtst, 8b)
-
-GEN_BINARY_TEST(cmhi, 2d)
-GEN_BINARY_TEST(cmhi, 4s)
-GEN_BINARY_TEST(cmhi, 2s)
-GEN_BINARY_TEST(cmhi, 8h)
-GEN_BINARY_TEST(cmhi, 4h)
-GEN_BINARY_TEST(cmhi, 16b)
-GEN_BINARY_TEST(cmhi, 8b)
-
-GEN_BINARY_TEST(cmgt, 2d)
-GEN_BINARY_TEST(cmgt, 4s)
-GEN_BINARY_TEST(cmgt, 2s)
-GEN_BINARY_TEST(cmgt, 8h)
-GEN_BINARY_TEST(cmgt, 4h)
-GEN_BINARY_TEST(cmgt, 16b)
-GEN_BINARY_TEST(cmgt, 8b)
-
-GEN_BINARY_TEST(cmhs, 2d)
-GEN_BINARY_TEST(cmhs, 4s)
-GEN_BINARY_TEST(cmhs, 2s)
-GEN_BINARY_TEST(cmhs, 8h)
-GEN_BINARY_TEST(cmhs, 4h)
-GEN_BINARY_TEST(cmhs, 16b)
-GEN_BINARY_TEST(cmhs, 8b)
-
-GEN_BINARY_TEST(cmge, 2d)
-GEN_BINARY_TEST(cmge, 4s)
-GEN_BINARY_TEST(cmge, 2s)
-GEN_BINARY_TEST(cmge, 8h)
-GEN_BINARY_TEST(cmge, 4h)
-GEN_BINARY_TEST(cmge, 16b)
-GEN_BINARY_TEST(cmge, 8b)
+GEN_BINARY_TEST(umax, 4s, 4s, 4s)
+GEN_BINARY_TEST(umax, 2s, 2s, 2s)
+GEN_BINARY_TEST(umax, 8h, 8h, 8h)
+GEN_BINARY_TEST(umax, 4h, 4h, 4h)
+GEN_BINARY_TEST(umax, 16b, 16b, 16b)
+GEN_BINARY_TEST(umax, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(umin, 4s, 4s, 4s)
+GEN_BINARY_TEST(umin, 2s, 2s, 2s)
+GEN_BINARY_TEST(umin, 8h, 8h, 8h)
+GEN_BINARY_TEST(umin, 4h, 4h, 4h)
+GEN_BINARY_TEST(umin, 16b, 16b, 16b)
+GEN_BINARY_TEST(umin, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(smax, 4s, 4s, 4s)
+GEN_BINARY_TEST(smax, 2s, 2s, 2s)
+GEN_BINARY_TEST(smax, 8h, 8h, 8h)
+GEN_BINARY_TEST(smax, 4h, 4h, 4h)
+GEN_BINARY_TEST(smax, 16b, 16b, 16b)
+GEN_BINARY_TEST(smax, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(smin, 4s, 4s, 4s)
+GEN_BINARY_TEST(smin, 2s, 2s, 2s)
+GEN_BINARY_TEST(smin, 8h, 8h, 8h)
+GEN_BINARY_TEST(smin, 4h, 4h, 4h)
+GEN_BINARY_TEST(smin, 16b, 16b, 16b)
+GEN_BINARY_TEST(smin, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(add, 2d, 2d, 2d)
+GEN_BINARY_TEST(add, 4s, 4s, 4s)
+GEN_BINARY_TEST(add, 2s, 2s, 2s)
+GEN_BINARY_TEST(add, 8h, 8h, 8h)
+GEN_BINARY_TEST(add, 4h, 4h, 4h)
+GEN_BINARY_TEST(add, 16b, 16b, 16b)
+GEN_BINARY_TEST(add, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(sub, 2d, 2d, 2d)
+GEN_BINARY_TEST(sub, 4s, 4s, 4s)
+GEN_BINARY_TEST(sub, 2s, 2s, 2s)
+GEN_BINARY_TEST(sub, 8h, 8h, 8h)
+GEN_BINARY_TEST(sub, 4h, 4h, 4h)
+GEN_BINARY_TEST(sub, 16b, 16b, 16b)
+GEN_BINARY_TEST(sub, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(mul, 4s, 4s, 4s)
+GEN_BINARY_TEST(mul, 2s, 2s, 2s)
+GEN_BINARY_TEST(mul, 8h, 8h, 8h)
+GEN_BINARY_TEST(mul, 4h, 4h, 4h)
+GEN_BINARY_TEST(mul, 16b, 16b, 16b)
+GEN_BINARY_TEST(mul, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(mla, 4s, 4s, 4s)
+GEN_BINARY_TEST(mla, 2s, 2s, 2s)
+GEN_BINARY_TEST(mla, 8h, 8h, 8h)
+GEN_BINARY_TEST(mla, 4h, 4h, 4h)
+GEN_BINARY_TEST(mla, 16b, 16b, 16b)
+GEN_BINARY_TEST(mla, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(mls, 4s, 4s, 4s)
+GEN_BINARY_TEST(mls, 2s, 2s, 2s)
+GEN_BINARY_TEST(mls, 8h, 8h, 8h)
+GEN_BINARY_TEST(mls, 4h, 4h, 4h)
+GEN_BINARY_TEST(mls, 16b, 16b, 16b)
+GEN_BINARY_TEST(mls, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(and, 16b, 16b, 16b)
+GEN_BINARY_TEST(and, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(bic, 16b, 16b, 16b)
+GEN_BINARY_TEST(bic, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(orr, 16b, 16b, 16b)
+GEN_BINARY_TEST(orr, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(orn, 16b, 16b, 16b)
+GEN_BINARY_TEST(orn, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(eor, 16b, 16b, 16b)
+GEN_BINARY_TEST(eor, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(bsl, 16b, 16b, 16b)
+GEN_BINARY_TEST(bsl, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(bit, 16b, 16b, 16b)
+GEN_BINARY_TEST(bit, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(bif, 16b, 16b, 16b)
+GEN_BINARY_TEST(bif, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(cmeq, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmeq, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmeq, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmeq, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmeq, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmeq, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmeq, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(cmtst, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmtst, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmtst, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmtst, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmtst, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmtst, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmtst, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(cmhi, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmhi, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmhi, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmhi, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmhi, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmhi, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmhi, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(cmgt, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmgt, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmgt, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmgt, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmgt, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmgt, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmgt, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(cmhs, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmhs, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmhs, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmhs, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmhs, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmhs, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmhs, 8b, 8b, 8b)
+
+GEN_BINARY_TEST(cmge, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmge, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmge, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmge, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmge, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmge, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmge, 8b, 8b, 8b)
GEN_SHIFT_TEST(ushr, 2d, 2d, 1)
GEN_SHIFT_TEST(ushr, 2d, 2d, 13)
@@ -975,213 +1088,118 @@
GEN_UNARY_TEST(xtn, 8b, 8h)
GEN_UNARY_TEST(xtn2, 16b, 8h)
+GEN_ONEINT_ONEVEC_TEST(umov_x_d0, "umov x9, v10.d[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_x_d1, "umov x9, v10.d[1]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_w_s0, "umov w9, v10.s[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_w_s3, "umov w9, v10.s[3]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_w_h0, "umov w9, v10.h[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_w_h7, "umov w9, v10.h[7]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_w_b0, "umov w9, v10.b[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_w_b15, "umov w9, v10.b[15]", 9, 10)
+
+GEN_ONEINT_ONEVEC_TEST(smov_x_s0, "smov x9, v10.s[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_x_s3, "smov x9, v10.s[3]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_x_h0, "smov x9, v10.h[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_x_h7, "smov x9, v10.h[7]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_w_h0, "smov w9, v10.h[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_w_h7, "smov w9, v10.h[7]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_x_b0, "smov x9, v10.b[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_x_b15, "smov x9, v10.b[15]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_w_b0, "smov w9, v10.b[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_w_b15, "smov w9, v10.b[15]", 9, 10)
-/* Generate a test that involves one integer reg and one vector reg,
- with no bias as towards which is input or output. */
-#define GEN_ONEINT_ONEVEC_TEST(TESTNAME,INSN,INTREGNO,VECREGNO) \
- __attribute__((noinline)) \
- static void test_##TESTNAME ( void ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[4]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0]); \
- randV128(&block[1]); \
- randV128(&block[2]); \
- randV128(&block[3]); \
- __asm__ __volatile__( \
- "ldr q"#VECREGNO", [%0, #0] ; " \
- "ldr x"#INTREGNO", [%0, #16] ; " \
- INSN " ; " \
- "str q"#VECREGNO", [%0, #32] ; " \
- "str x"#INTREGNO", [%0, #48] ; " \
- : : "r"(&block[0]) : "memory", "v"#VECREGNO, "x"#INTREGNO \
- ); \
- printf(INSN " "); \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf(" "); \
- showV128(&block[2]); printf(" "); \
- showV128(&block[3]); printf("\n"); \
- } \
- }
+GEN_TWOVEC_TEST(fcvtn_2s_2d, "fcvtn v22.2s, v23.2d", 22, 23)
+GEN_TWOVEC_TEST(fcvtn_4s_2d, "fcvtn2 v22.4s, v23.2d", 22, 23)
-GEN_ONEINT_ONEVEC_TEST(umov_01, "umov x9, v10.d[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_02, "umov x9, v10.d[1]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_03, "umov w9, v10.s[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_04, "umov w9, v10.s[3]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_05, "umov w9, v10.h[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_06, "umov w9, v10.h[7]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_07, "umov w9, v10.b[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_08, "umov w9, v10.b[15]", 9, 10)
-
-GEN_ONEINT_ONEVEC_TEST(smov_01, "smov x9, v10.s[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_02, "smov x9, v10.s[3]", 9, 10)
-
-GEN_ONEINT_ONEVEC_TEST(smov_03, "smov x9, v10.h[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_04, "smov x9, v10.h[7]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_05, "smov w9, v10.h[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_06, "smov w9, v10.h[7]", 9, 10)
-
-GEN_ONEINT_ONEVEC_TEST(smov_07, "smov x9, v10.b[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_08, "smov x9, v10.b[15]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_09, "smov w9, v10.b[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_10, "smov w9, v10.b[15]", 9, 10)
+GEN_UNARY_TEST(neg, 2d, 2d)
+GEN_UNARY_TEST(neg, 4s, 4s)
+GEN_UNARY_TEST(neg, 2s, 2s)
+GEN_UNARY_TEST(neg, 8h, 8h)
+GEN_UNARY_TEST(neg, 4h, 4h)
+GEN_UNARY_TEST(neg, 16b, 16b)
+GEN_UNARY_TEST(neg, 8b, 8b)
-/* Generate a test that involves two vector regs,
- with no bias as towards which is input or output. */
-#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \
- __attribute__((noinline)) \
- static void test_##TESTNAME ( void ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[4]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0]); \
- randV128(&block[1]); \
- randV128(&block[2]); \
- randV128(&block[3]); \
- __asm__ __volatile__( \
- "ldr q"#VECREG1NO", [%0, #0] ; " \
- "ldr q"#VECREG2NO", [%0, #16] ; " \
- INSN " ; " \
- "str q"#VECREG1NO", [%0, #32] ; " \
- "str q"#VECREG2NO", [%0, #48] ; " \
- : : "r"(&block[0]) : "memory", "v"#VECREG1NO, "v"#VECREG2NO \
- ); \
- printf(INSN " "); \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf(" "); \
- showV128(&block[2]); printf(" "); \
- showV128(&block[3]); printf("\n"); \
- } \
- }
-
-GEN_TWOVEC_TEST(fcvtn_01, "fcvtn v22.2s, v23.2d", 22, 23)
-GEN_TWOVEC_TEST(fcvtn_02, "fcvtn2 v22.4s, v23.2d", 22, 23)
-
-GEN_UNARY_TEST(neg, 2d, 2d)
-GEN_UNARY_TEST(neg, 4s, 4s)
-GEN_UNARY_TEST(neg, 2s, 2s)
-GEN_UNARY_TEST(neg, 8h, 8h)
-GEN_UNARY_TEST(neg, 4h, 4h)
-GEN_UNARY_TEST(neg, 16b, 16b)
-GEN_UNARY_TEST(neg, 8b, 8b)
-GEN_BINARY_TEST(fadd, 2d)
-GEN_BINARY_TEST(fadd, 4s)
-GEN_BINARY_TEST(fadd, 2s)
-GEN_BINARY_TEST(fsub, 2d)
-GEN_BINARY_TEST(fsub, 4s)
-GEN_BINARY_TEST(fsub, 2s)
-GEN_BINARY_TEST(fmul, 2d)
-GEN_BINARY_TEST(fmul, 4s)
-GEN_BINARY_TEST(fmul, 2s)
-GEN_BINARY_TEST(fdiv, 2d)
-GEN_BINARY_TEST(fdiv, 4s)
-GEN_BINARY_TEST(fdiv, 2s)
-GEN_BINARY_TEST(fmla, 2d)
-GEN_BINARY_TEST(fmla, 4s)
-GEN_BINARY_TEST(fmla, 2s)
-GEN_BINARY_TEST(fmls, 2d)
-GEN_BINARY_TEST(fmls, 4s)
-GEN_BINARY_TEST(fmls, 2s)
-GEN_BINARY_TEST(fabd, 2d)
-GEN_BINARY_TEST(fabd, 4s)
-GEN_BINARY_TEST(fabd, 2s)
-
-/* Generate a test that involves three vector regs,
- with no bias as towards which is input or output. It's also OK
- to use v16, v17, v18 as scratch. */
-#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \
- __attribute__((noinline)) \
- static void test_##TESTNAME ( void ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[6]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0]); \
- randV128(&block[1]); \
- randV128(&block[2]); \
- randV128(&block[3]); \
- randV128(&block[4]); \
- randV128(&block[5]); \
- __asm__ __volatile__( \
- "ldr q"#VECREG1NO", [%0, #0] ; " \
- "ldr q"#VECREG2NO", [%0, #16] ; " \
- "ldr q"#VECREG3NO", [%0, #32] ; " \
- INSN " ; " \
- "str q"#VECREG1NO", [%0, #48] ; " \
- "str q"#VECREG2NO", [%0, #64] ; " \
- "str q"#VECREG3NO", [%0, #80] ; " \
- : : "r"(&block[0]) \
- : "memory", "v"#VECREG1NO, "v"#VECREG2NO, "v"#VECREG3NO, \
- "v16", "v17", "v18" \
- ); \
- printf(INSN " "); \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf(" "); \
- showV128(&block[2]); printf(" "); \
- showV128(&block[3]); printf(" "); \
- showV128(&block[4]); printf(" "); \
- showV128(&block[5]); printf("\n"); \
- } \
- }
+GEN_BINARY_TEST(fadd, 2d, 2d, 2d)
+GEN_BINARY_TEST(fadd, 4s, 4s, 4s)
+GEN_BINARY_TEST(fadd, 2s, 2s, 2s)
+GEN_BINARY_TEST(fsub, 2d, 2d, 2d)
+GEN_BINARY_TEST(fsub, 4s, 4s, 4s)
+GEN_BINARY_TEST(fsub, 2s, 2s, 2s)
+GEN_BINARY_TEST(fmul, 2d, 2d, 2d)
+GEN_BINARY_TEST(fmul, 4s, 4s, 4s)
+GEN_BINARY_TEST(fmul, 2s, 2s, 2s)
+GEN_BINARY_TEST(fdiv, 2d, 2d, 2d)
+GEN_BINARY_TEST(fdiv, 4s, 4s, 4s)
+GEN_BINARY_TEST(fdiv, 2s, 2s, 2s)
+GEN_BINARY_TEST(fmla, 2d, 2d, 2d)
+GEN_BINARY_TEST(fmla, 4s, 4s, 4s)
+GEN_BINARY_TEST(fmla, 2s, 2s, 2s)
+GEN_BINARY_TEST(fmls, 2d, 2d, 2d)
+GEN_BINARY_TEST(fmls, 4s, 4s, 4s)
+GEN_BINARY_TEST(fmls, 2s, 2s, 2s)
+GEN_BINARY_TEST(fabd, 2d, 2d, 2d)
+GEN_BINARY_TEST(fabd, 4s, 4s, 4s)
+GEN_BINARY_TEST(fabd, 2s, 2s, 2s)
GEN_THREEVEC_TEST(add_d_d_d, "add d21, d22, d23", 21, 22, 23)
GEN_THREEVEC_TEST(sub_d_d_d, "sub d21, d22, d23", 21, 22, 23)
/* overkill -- don't need two vecs, only one */
-GEN_TWOVEC_TEST(fmov_scalar_imm_01, "fmov d22, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_scalar_imm_02, "fmov d22, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_scalar_imm_03, "fmov d22, #1.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_scalar_imm_04, "fmov s22, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_scalar_imm_05, "fmov s22, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_scalar_imm_06, "fmov s22, #-1.0", 22, 23)
-
-GEN_ONEINT_ONEVEC_TEST(fmov_gen_01, "fmov s7, w15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_gen_02, "fmov d7, x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_gen_03, "fmov v7.d[1], x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_gen_04, "fmov w15, s7", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_gen_05, "fmov x15, d7", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_gen_06, "fmov x15, v7.d[1]", 15, 7)
-
-GEN_TWOVEC_TEST(movi_vector_imm_01, "fmov d22, #0.125", 22, 23)
-GEN_TWOVEC_TEST(movi_vector_imm_02, "fmov d22, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(movi_vector_imm_03, "fmov d22, #1.0", 22, 23)
-GEN_TWOVEC_TEST(movi_vector_imm_04, "fmov v22.2d, #0.125", 22, 23)
-GEN_TWOVEC_TEST(movi_vector_imm_05, "fmov v22.2d, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(movi_vector_imm_06, "fmov v22.2d, #1.0", 22, 23)
-
-GEN_ONEINT_ONEVEC_TEST(sucvtf_01, "scvtf s7, w15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_02, "scvtf d7, w15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_03, "scvtf s7, x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_04, "scvtf d7, x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_05, "ucvtf s7, w15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_06, "ucvtf d7, w15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_07, "ucvtf s7, x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(sucvtf_08, "ucvtf d7, x15", 15, 7)
-
-GEN_THREEVEC_TEST(fadd_d, "fadd d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fadd_s, "fadd s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fsub_d, "fsub d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fsub_s, "fsub s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_d, "fmul d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_s, "fmul s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fdiv_d, "fdiv d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fdiv_s, "fdiv s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fnmul_d, "fnmul d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fnmul_s, "fnmul s2, s11, s29", 2, 11, 29)
-
-GEN_THREEVEC_TEST(fabd_d, "fabd d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fabd_s, "fabd s2, s11, s29", 2, 11, 29)
-
-GEN_TWOVEC_TEST(fmov_d, "fmov d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fmov_s, "fmov s22, s23", 22, 23)
-GEN_TWOVEC_TEST(fabs_d, "fabs d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fabs_s, "fabs s22, s23", 22, 23)
-GEN_TWOVEC_TEST(fneg_d, "fneg d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fneg_s, "fneg s22, s23", 22, 23)
-GEN_TWOVEC_TEST(fsqrt_d, "fsqrt d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fsqrt_s, "fsqrt s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fmov_d_imm_01, "fmov d22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_d_imm_02, "fmov d22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_d_imm_03, "fmov d22, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_imm_01, "fmov s22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_imm_02, "fmov s22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_imm_03, "fmov s22, #-1.0", 22, 23)
+
+GEN_ONEINT_ONEVEC_TEST(fmov_s_w, "fmov s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_d_x, "fmov d7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_d1_x, "fmov v7.d[1], x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_w_s, "fmov w15, s7", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_x_d, "fmov x15, d7", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_x_d1, "fmov x15, v7.d[1]", 15, 7)
+
+GEN_TWOVEC_TEST(fmov_2d_imm_01, "fmov v22.2d, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_2d_imm_02, "fmov v22.2d, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_2d_imm_03, "fmov v22.2d, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_4s_imm_01, "fmov v22.4s, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_4s_imm_02, "fmov v22.4s, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_4s_imm_03, "fmov v22.4s, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_2s_imm_01, "fmov v22.2s, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_2s_imm_02, "fmov v22.2s, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_2s_imm_03, "fmov v22.2s, #1.0", 22, 23)
+
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_w, "scvtf s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_w, "scvtf d7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_s_x, "scvtf s7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(scvtf_d_x, "scvtf d7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w, "ucvtf s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w, "ucvtf d7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x, "ucvtf s7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x, "ucvtf d7, x15", 15, 7)
+
+GEN_THREEVEC_TEST(fadd_d_d_d, "fadd d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fadd_s_s_s, "fadd s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fsub_d_d_d, "fsub d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fsub_s_s_s, "fsub s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fdiv_d_d_d, "fdiv d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fdiv_s_s_s, "fdiv s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fnmul_d_d_d, "fnmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fnmul_s_s_s, "fnmul s2, s11, s29", 2, 11, 29)
+
+GEN_THREEVEC_TEST(fabd_d_d_d, "fabd d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fabd_s_s_s, "fabd s2, s11, s29", 2, 11, 29)
+
+GEN_TWOVEC_TEST(fmov_d_d, "fmov d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_s, "fmov s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fabs_d_d, "fabs d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fabs_s_s, "fabs s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fneg_d_d, "fneg d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fneg_s_s, "fneg s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_d_d, "fsqrt d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_s_s, "fsqrt s22, s23", 22, 23)
GEN_UNARY_TEST(fneg, 2d, 2d)
GEN_UNARY_TEST(fneg, 4s, 4s)
@@ -1190,21 +1208,21 @@
GEN_UNARY_TEST(fabs, 4s, 4s)
GEN_UNARY_TEST(fabs, 2s, 2s)
-GEN_BINARY_TEST(fcmeq, 2d)
-GEN_BINARY_TEST(fcmeq, 4s)
-GEN_BINARY_TEST(fcmeq, 2s)
-GEN_BINARY_TEST(fcmge, 2d)
-GEN_BINARY_TEST(fcmge, 4s)
-GEN_BINARY_TEST(fcmge, 2s)
-GEN_BINARY_TEST(fcmgt, 2d)
-GEN_BINARY_TEST(fcmgt, 4s)
-GEN_BINARY_TEST(fcmgt, 2s)
-GEN_BINARY_TEST(facge, 2d)
-GEN_BINARY_TEST(facge, 4s)
-GEN_BINARY_TEST(facge, 2s)
-GEN_BINARY_TEST(facgt, 2d)
-GEN_BINARY_TEST(facgt, 4s)
-GEN_BINARY_TEST(facgt, 2s)
+GEN_BINARY_TEST(fcmeq, 2d, 2d, 2d)
+GEN_BINARY_TEST(fcmeq, 4s, 4s, 4s)
+GEN_BINARY_TEST(fcmeq, 2s, 2s, 2s)
+GEN_BINARY_TEST(fcmge, 2d, 2d, 2d)
+GEN_BINARY_TEST(fcmge, 4s, 4s, 4s)
+GEN_BINARY_TEST(fcmge, 2s, 2s, 2s)
+GEN_BINARY_TEST(fcmgt, 2d, 2d, 2d)
+GEN_BINARY_TEST(fcmgt, 4s, 4s, 4s)
+GEN_BINARY_TEST(fcmgt, 2s, 2s, 2s)
+GEN_BINARY_TEST(facge, 2d, 2d, 2d)
+GEN_BINARY_TEST(facge, 4s, 4s, 4s)
+GEN_BINARY_TEST(facge, 2s, 2s, 2s)
+GEN_BINARY_TEST(facgt, 2d, 2d, 2d)
+GEN_BINARY_TEST(facgt, 4s, 4s, 4s)
+GEN_BINARY_TEST(facgt, 2s, 2s, 2s)
// Uses v15 as the first table entry
GEN_THREEVEC_TEST(
@@ -1280,515 +1298,1084 @@
"tbx v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b",
21, 15, 23)
-GEN_TWOVEC_TEST(cmge_zero_2d, "cmge v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_4s, "cmge v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_2s, "cmge v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_8h, "cmge v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_4h, "cmge v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_16b, "cmge v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_8b, "cmge v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmgt_zero_2d, "cmgt v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_4s, "cmgt v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_2s, "cmgt v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_8h, "cmgt v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_4h, "cmgt v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_16b, "cmgt v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_8b, "cmgt v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmle_zero_2d, "cmle v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_4s, "cmle v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_2s, "cmle v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_8h, "cmle v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_4h, "cmle v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_16b, "cmle v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_8b, "cmle v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmeq_zero_2d, "cmeq v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_4s, "cmeq v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_2s, "cmeq v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_8h, "cmeq v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_4h, "cmeq v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_16b, "cmeq v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_8b, "cmeq v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmlt_zero_2d, "cmlt v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_4s, "cmlt v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_2s, "cmlt v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_8h, "cmlt v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_4h, "cmlt v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_16b, "cmlt v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_8b, "cmlt v5.8b, v22.8b, #0", 5, 22)
-
+GEN_TWOVEC_TEST(cmge_zero_2d_2d, "cmge v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_4s_4s, "cmge v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_2s_2s, "cmge v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_8h_8h, "cmge v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_4h_4h, "cmge v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_16b_16b, "cmge v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_8b_8b, "cmge v5.8b, v22.8b, #0", 5, 22)
+
+GEN_TWOVEC_TEST(cmgt_zero_2d_2d, "cmgt v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_4s_4s, "cmgt v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_2s_2s, "cmgt v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_8h_8h, "cmgt v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_4h_4h, "cmgt v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_16b_16b, "cmgt v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_8b_8b, "cmgt v5.8b, v22.8b, #0", 5, 22)
+
+GEN_TWOVEC_TEST(cmle_zero_2d_2d, "cmle v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_4s_4s, "cmle v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_2s_2s, "cmle v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_8h_8h, "cmle v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_4h_4h, "cmle v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_16b_16b, "cmle v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_8b_8b, "cmle v5.8b, v22.8b, #0", 5, 22)
+
+GEN_TWOVEC_TEST(cmeq_zero_2d_2d, "cmeq v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_4s_4s, "cmeq v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_2s_2s, "cmeq v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_8h_8h, "cmeq v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_4h_4h, "cmeq v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_16b_16b, "cmeq v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_8b_8b, "cmeq v5.8b, v22.8b, #0", 5, 22)
+
+GEN_TWOVEC_TEST(cmlt_zero_2d_2d, "cmlt v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_4s_4s, "cmlt v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_2s_2s, "cmlt v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_8h_8h, "cmlt v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_4h_4h, "cmlt v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_16b_16b, "cmlt v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_8b_8b, "cmlt v5.8b, v22.8b, #0", 5, 22)
+
+
+/* ---------------------------------------------------------------- */
+/* -- main() -- */
+/* ---------------------------------------------------------------- */
-
-/* IMPORTANT: keep the tests in here in the same order as the
- implementations are in guest_arm64_toIR.c. */
int main ( void )
{
assert(sizeof(V128) == 16);
- printf("BEGIN: FMOV (general)\n");
- test_fmov_gen_01();
- test_fmov_gen_02();
- test_fmov_gen_03();
- test_fmov_gen_04();
- test_fmov_gen_05();
- test_fmov_gen_06();
- printf("END: FMOV (general)\n\n");
-
- printf("BEGIN: FMOV (scalar, immediate)\n");
- test_fmov_scalar_imm_01();
- test_fmov_scalar_imm_02();
- test_fmov_scalar_imm_03();
- test_fmov_scalar_imm_04();
- test_fmov_scalar_imm_05();
- test_fmov_scalar_imm_06();
- printf("END: FMOV (scalar, immediate)\n\n");
-
- printf("BEGIN: {FMOV,MOVI} (vector, immediate)\n");
- test_movi_vector_imm_01();
- test_movi_vector_imm_02();
- test_movi_vector_imm_03();
- test_movi_vector_imm_04();
- test_movi_vector_imm_05();
- test_movi_vector_imm_06();
- printf("END: {FMOV,MOVI} (vector, immediate)\n\n");
-
- printf("BEGIN: {S,U}CVTF (scalar, integer)\n");
- test_sucvtf_01();
- test_sucvtf_02();
- test_sucvtf_03();
- test_sucvtf_04();
- test_sucvtf_05();
- test_sucvtf_06();
- test_sucvtf_07();
- test_sucvtf_08();
- printf("END: {S,U}CVTF (scalar, integer)\n\n");
-
- printf("BEGIN: F{ADD,SUB,MUL,DIV,NMUL} (scalar)\n");
- test_fadd_d();
- test_fadd_s();
- test_fsub_d();
- test_fsub_s();
- test_fmul_d();
- test_fmul_s();
- test_fdiv_d();
- test_fdiv_s();
- test_fnmul_d();
- test_fnmul_s();
- printf("END: F{ADD,SUB,MUL,DIV,NMUL} (scalar)\n\n");
-
- printf("BEGIN: F{MOV,ABS,NEG,SQRT} D/D or S/S\n");
- test_fmov_d();
- test_fmov_s();
- test_fabs_d();
- test_fabs_s();
- test_fneg_d();
- test_fneg_s();
- test_fsqrt_d();
- test_fsqrt_s();
- printf("END: F{MOV,ABS,NEG,SQRT} D/D or S/S\n\n");
-
- printf("BEGIN: F{ABS,NEG} (vector)\n");
- test_fabs_2d_2d();
- test_fabs_4s_4s();
- test_fabs_2s_2s();
- test_fneg_2d_2d();
- test_fneg_4s_4s();
- test_fneg_2s_2s();
- printf("END: F{ABS,NEG} (vector)\n\n");
-
- printf("FCMP,FCMPE MISSING\n\n");
-
- printf("F{N}M{ADD,SUB} MISSING\n\n");
-
- printf("FCVT{N,P,M,Z}{S,U} (scalar, integer) MISSING\n\n");
-
- printf("FRINT{I,M,P,Z} (scalar) MISSING\n\n");
-
- printf("FCVT (scalar) MISSING\n\n");
-
- printf("BEGIN: FABD (scalar) MISSING\n");
- test_fabd_d();
- test_fabd_s();
- printf("END: FABD (scalar) MISSING\n\n");
-
- printf("{S,U}CVTF (vector, integer) MISSING\n\n");
-
- printf("BEGIN: F{ADD,SUB,MUL,DIV,MLA,MLS,ABD} (vector)\n");
- test_fadd_2d();
- test_fadd_4s();
- test_fadd_2s();
- test_fsub_2d();
- test_fsub_4s();
- test_fsub_2s();
- test_fmul_2d();
- test_fmul_4s();
- test_fmul_2s();
- test_fdiv_2d();
- test_fdiv_4s();
- test_fdiv_2s();
- test_fmla_2d();
- test_fmla_4s();
- test_fmla_2s();
- test_fmls_2d();
- test_fmls_4s();
- test_fmls_2s();
- test_fabd_2d();
- test_fabd_4s();
- test_fabd_2s();
- printf("END: F{ADD,SUB,MUL,DIV,MLA,MLS,ABD} (vector)\n\n");
-
- printf("BEGIN: FCM{EQ,GE,GT}, FAC{GE,GT} (vector)\n");
- test_fcmeq_2d();
- test_fcmeq_4s();
- test_fcmeq_2s();
- test_fcmge_2d();
- test_fcmge_4s();
- test_fcmge_2s();
- test_fcmgt_2d();
- test_fcmgt_4s();
- test_fcmgt_2s();
- test_facge_2d();
- test_facge_4s();
- test_facge_2s();
- test_facgt_2d();
- test_facgt_4s();
- test_facgt_2s();
- printf("END: FCM{EQ,GE,GT}, FAC{GE,GT} (vector)\n");
-
- printf("BEGIN: FCVTN (MISSING 16F <- 32F cases)\n");
- test_fcvtn_01();
- test_fcvtn_02();
- printf("END: FCVTN (MISSING 16F <- 32F cases)\n\n");
-
- printf("BEGIN: ADD/SUB (vector)\n");
- test_add_2d();
- test_add_4s();
- test_add_2s();
- test_add_8h();
- test_add_4h();
- test_add_16b();
- test_add_8b();
- test_sub_2d();
- test_sub_4s();
- test_sub_2s();
- test_sub_8h();
- test_sub_4h();
- test_sub_16b();
- test_sub_8b();
- printf("END: ADD/SUB (vector)\n\n");
-
- printf("BEGIN: ADD/SUB (scalar)\n");
- test_add_d_d_d();
- test_sub_d_d_d();
- printf("END: ADD/SUB (scalar)\n\n");
-
- printf("BEGIN: MUL/PMUL/MLA/MLS (vector)\n");
- test_mul_4s();
- test_mul_2s();
- test_mul_8h();
- test_mul_4h();
- test_mul_16b();
- test_mul_8b();
- test_mla_4s();
- test_mla_2s();
- test_mla_8h();
- test_mla_4h();
- test_mla_16b();
- test_mla_8b();
- test_mls_4s();
- test_mls_2s();
- test_mls_8h();
- test_mls_4h();
- test_mls_16b();
- test_mls_8b();
- printf("END: MUL/PMUL/MLA/MLS (vector) (MISSING PMUL)\n\n");
-
- printf("BEGIN: {S,U}{MIN,MAX} (vector)\n");
- test_umax_4s();
- test_umax_8h();
- test_umax_4h();
- test_umax_16b();
- test_umax_8b();
- test_umin_4s();
- test_umin_8h();
- test_umin_4h();
- test_umin_16b();
- test_umin_8b();
- test_smax_4s();
- test_smax_8h();
- test_smax_4h();
- test_smax_16b();
- test_smax_8b();
- test_smin_4s();
- test_smin_8h();
- test_smin_4h();
- test_smin_16b();
- test_smin_8b();
- printf("END: {S,U}{MIN,MAX} (vector)\n\n");
+ // ======================== FP ========================
- printf("BEGIN: {S,U}{MIN,MAX}V\n");
- test_UMINV();
- test_UMAXV();
- test_SMINV();
- test_SMAXV();
- printf("END: {S,U}{MIN,MAX}V\n\n");
+ // fabs d,s
+ // fabs 2d,4s,2s
+ test_fabs_d_d(TyDF);
+ test_fabs_s_s(TySF);
+ test_fabs_2d_2d(TyDF);
+ test_fabs_4s_4s(TySF);
+ test_fabs_2s_2s(TyDF);
+ test_fneg_2d_2d(TySF);
+ test_fneg_4s_4s(TyDF);
+ test_fneg_2s_2s(TySF);
+
+ // fneg d,s
+ // fneg 2d,4s,2s
+ test_fneg_d_d(TyDF);
+ test_fneg_s_s(TySF);
+
+ // fsqrt d,s
+ // fsqrt 2d,4s,2s
+ test_fsqrt_d_d(TyDF);
+ test_fsqrt_s_s(TySF);
+
+ // fadd d,s
+ // fsub d,s
+ test_fadd_d_d_d(TyDF);
+ test_fadd_s_s_s(TySF);
+ test_fsub_d_d_d(TyDF);
+ test_fsub_s_s_s(TySF);
+
+ // fadd 2d,4s,2s
+ // fsub 2d,4s,2s
+ test_fadd_2d_2d_2d(TyDF);
+ test_fadd_4s_4s_4s(TySF);
+ test_fadd_2s_2s_2s(TySF);
+ test_fsub_2d_2d_2d(TyDF);
+ test_fsub_4s_4s_4s(TySF);
+ test_fsub_2s_2s_2s(TySF);
+
+ // fabd d,s
+ // fabd 2d,4s,2s
+ test_fabd_d_d_d(TyDF);
+ test_fabd_s_s_s(TySF);
+ test_fabd_2d_2d_2d(TyDF);
+ test_fabd_4s_4s_4s(TySF);
+ test_fabd_2s_2s_2s(TySF);
+
+ // faddp d,s (floating add pair)
+ // faddp 2d,4s,2s
+
+ // fccmp d,s (floating point conditional quiet compare)
+ // fccmpe d,s (floating point conditional signaling compare)
+
+ // fcmeq d,s
+ // fcmge d,s
+ // fcmgt d,s
+ // facgt d,s (floating abs compare GE)
+ // facge d,s (floating abs compare GE)
+
+ // fcmeq 2d,4s,2s
+ // fcmge 2d,4s,2s
+ // fcmgt 2d,4s,2s
+ // facge 2d,4s,2s
+ // facgt 2d,4s,2s
+ test_fcmeq_2d_2d_2d(TyDF);
+ test_fcmeq_4s_4s_4s(TySF);
+ test_fcmeq_2s_2s_2s(TySF);
+ test_fcmge_2d_2d_2d(TyDF);
+ test_fcmge_4s_4s_4s(TySF);
+ test_fcmge_2s_2s_2s(TySF);
+ test_fcmgt_2d_2d_2d(TyDF);
+ test_fcmgt_4s_4s_4s(TySF);
+ test_fcmgt_2s_2s_2s(TySF);
+ test_facge_2d_2d_2d(TyDF);
+ test_facge_4s_4s_4s(TySF);
+ test_facge_2s_2s_2s(TySF);
+ test_facgt_2d_2d_2d(TyDF);
+ test_facgt_4s_4s_4s(TySF);
+ test_facgt_2s_2s_2s(TySF);
+
+ // fcmeq_z d,s
+ // fcmge_z d,s
+ // fcmgt_z d,s
+ // fcmle_z d,s
+ // fcmlt_z d,s
+
+ // fcmeq_z 2d,4s,2s
+ // fcmge_z 2d,4s,2s
+ // fcmgt_z 2d,4s,2s
+ // fcmle_z 2d,4s,2s
+ // fcmlt_z 2d,4s,2s
+
+ // fcmp_z d,s
+ // fcmpe_z d,s
+ // fcmp d,s (floating point quiet, set flags)
+ // fcmpe d,s (floating point signaling, set flags)
+
+ // fcsel d,s (fp cond select)
+
+ // fdiv d,s
+ // fdiv 2d,4s,2s
+ test_fdiv_d_d_d(TyDF);
+ test_fdiv_s_s_s(TySF);
+ test_fdiv_2d_2d_2d(TyDF);
+ test_fdiv_4s_4s_4s(TySF);
+ test_fdiv_2s_2s_2s(TySF);
+
+ // fmadd d,s
+ // fnmadd d,s
+ // fmsub d,s
+ // fnmsub d,s
+
+ // fnmul d,s
+ test_fnmul_d_d_d(TyDF);
+ test_fnmul_s_s_s(TySF);
+
+ // fmax d,s
+ // fmin d,s
+ // fmaxnm d,s ("max number")
+ // fminnm d,s
+
+ // fmax 2d,4s,2s
+ // fmin 2d,4s,2s
+ // fmaxnm 2d,4s,2s
+ // fminnm 2d,4s,2s
+
+ // fmaxnmp d_2d,s_2s ("max number pairwise")
+ // fminnmp d_2d,s_2s
+
+ // fmaxnmp 2d,4s,2s
+ // fminnmp 2d,4s,2s
+
+ // fmaxnmv s_4s (maxnum across vector)
+ // fminnmv s_4s
+
+ // fmaxp d_2d,s_2s (max of a pair)
+ // fminp d_2d,s_2s (max of a pair)
+
+ // fmaxp 2d,4s,2s (max pairwise)
+ // fminp 2d,4s,2s
+
+ // fmaxv s_4s (max across vector)
+ // fminv s_4s
+
+ // fmla 2d,4s,2s
+ // fmls 2d,4s,2s
+ test_fmla_2d_2d_2d(TyDF);
+ test_fmla_4s_4s_4s(TySF);
+ test_fmla_2s_2s_2s(TySF);
+ test_fmls_2d_2d_2d(TyDF);
+ test_fmls_4s_4s_4s(TySF);
+ test_fmls_2s_2s_2s(TySF);
+
+ // fmla d_d_d[],s_s_s[] (by element)
+ // fmls d_d_d[],s_s_s[] (by element)
+
+ // fmla 2d_2d_d[],4s_4s_s[],2s_2s_s[]
+ // fmls 2d_2d_d[],4s_4s_s[],2s_2s_s[]
+
+ // fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group)
+ // INCOMPLETE
+ test_fmov_2d_imm_01(TyD);
+ test_fmov_2d_imm_02(TyD);
+ test_fmov_2d_imm_03(TyD);
+ if (0) test_fmov_4s_imm_01(TyS);
+ if (0) test_fmov_4s_imm_02(TyS);
+ if (0) test_fmov_4s_imm_03(TyS);
+ if (0) test_fmov_2s_imm_01(TyS);
+ if (0) test_fmov_2s_imm_02(TyS);
+ if (0) test_fmov_2s_imm_03(TyS);
+
+ // fmov d_d,s_s
+ test_fmov_d_d(TyDF);
+ test_fmov_s_s(TySF);
+
+ // fmov s_w,w_s,d_x,d[1]_x,x_d,x_d[1]
+ test_fmov_s_w(TyS);
+ test_fmov_d_x(TyD);
+ test_fmov_d1_x(TyD);
+ test_fmov_w_s(TyS);
+ test_fmov_x_d(TyD);
+ test_fmov_x_d1(TyD);
+
+ // fmov d,s #imm
+ test_fmov_d_imm_01(TyNONE);
+ test_fmov_d_imm_02(TyNONE);
+ test_fmov_d_imm_03(TyNONE);
+ test_fmov_s_imm_01(TyNONE);
+ test_fmov_s_imm_02(TyNONE);
+ test_fmov_s_imm_03(TyNONE);
+
+ // fmul d_d_d[],s_s_s[]
+ // fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[]
+
+ // fmul 2d,4s,2s
+ // fmul d,s
+ test_fmul_d_d_d(TyDF);
+ test_fmul_s_s_s(TySF);
+ test_fmul_2d_2d_2d(TyDF);
+ test_fmul_4s_4s_4s(TySF);
+ test_fmul_2s_2s_2s(TySF);
+
+ // fmulx d_d_d[],s_s_s[]
+ // fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
+
+ // fmulx d,s
+ // fmulx 2d,4s,2s
+
+ // frecpe d,s (recip estimate)
+ // frecpe 2d,4s,2s
+
+ // frecps d,s (recip step)
+ // frecps 2d,4s,2s
+
+ // frecpx d,s (recip exponent)
+
+ // frinta d,s
+ // frinti d,s
+ // frintm d,s
+ // frintn d,s
+ // frintp d,s
+ // frintx d,s
+ // frintz d,s
+
+ // frinta 2d,4s,2s (round to integral, nearest away)
+ // frinti 2d,4s,2s (round to integral, per FPCR)
+ // frintm 2d,4s,2s (round to integral, minus inf)
+ // frintn 2d,4s,2s (round to integral, nearest, to even)
+ // frintp 2d,4s,2s (round to integral, plus inf)
+ // frintx 2d,4s,2s (round to integral exact, per FPCR)
+ // frintz 2d,4s,2s (round to integral, zero)
+
+ // frsqrte d,s (est)
+ // frsqrte 2d,4s,2s
+
+ // frsqrts d,s (step)
+ // frsqrts 2d,4s,2s
+
+ // ======================== CONV ========================
+
+ // fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
+
+ // fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
+
+ // fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
+ // INCOMPLETE
+ test_fcvtn_2s_2d(TyDF);
+ test_fcvtn_4s_2d(TyDF);
+
+ // fcvtas d,s (fcvt to signed int, nearest, ties away)
+ // fcvtau d,s (fcvt to unsigned int, nearest, ties away)
+ //...
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