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From: <sv...@va...> - 2013-10-23 14:07:27
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Author: dejanj
Date: Wed Oct 23 14:07:15 2013
New Revision: 13687
Log:
mips32: Change the tests values so that the result is
the same on all mips32 platforms. Add extra cases in
vbit-test for mips32.
Added:
trunk/none/tests/mips32/mips32_dsp.stdout.exp-LE
Modified:
trunk/memcheck/tests/vbit-test/irops.c
trunk/none/tests/mips32/Makefile.am
trunk/none/tests/mips32/mips32_dsp.c
trunk/none/tests/mips32/mips32_dsp.stdout.exp
trunk/none/tests/mips32/mips32_dsp.stdout.exp-BE
trunk/none/tests/mips32/mips32_dspr2.c
trunk/none/tests/mips32/mips32_dspr2.stdout.exp
Modified: trunk/memcheck/tests/vbit-test/irops.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/irops.c (original)
+++ trunk/memcheck/tests/vbit-test/irops.c Wed Oct 23 14:07:15 2013
@@ -10,30 +10,30 @@
That is not necessary but helpful when supporting a new architecture.
*/
static irop_t irops[] = {
- { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
- { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Add32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Add64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Sub32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Sub64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
{ DEFOP(Iop_Mul8, UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_Mul16, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_Mul32, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Mul64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
- { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
- { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
- { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
@@ -47,7 +47,7 @@
{ DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
{ DEFOP(Iop_CmpEQ8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_CmpEQ16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_CmpEQ16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_CmpEQ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_CmpEQ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
{ DEFOP(Iop_CmpNE8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
@@ -57,7 +57,7 @@
{ DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_Not32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_CasCmpEQ8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
@@ -76,23 +76,23 @@
{ DEFOP(Iop_MullS32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
// s390 has signed multiplication of 64-bit values but the result
// is 64-bit (not 128-bit). So we cannot test this op standalone.
- { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
- { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc, mips assert
- { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc, mips assert
- { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
- { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
+ { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts
+ { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
+ { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
+ { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts
{ DEFOP(Iop_CmpNEZ8, UNDEF_ALL), }, // not supported by mc_translate
{ DEFOP(Iop_CmpNEZ16, UNDEF_ALL), }, // not supported by mc_translate
{ DEFOP(Iop_CmpNEZ32, UNDEF_ALL), }, // not supported by mc_translate
@@ -118,8 +118,8 @@
{ DEFOP(Iop_DivS32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
// On s390 the DivMod operations always appear in a certain context
// So they cannot be tested in isolation on that platform.
- { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_DivModS64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
@@ -129,20 +129,20 @@
{ DEFOP(Iop_16Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_16Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
{ DEFOP(Iop_32Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_8Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_8Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
{ DEFOP(Iop_16Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_16Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
{ DEFOP(Iop_32Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_64to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_64to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_8HLto16, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel
{ DEFOP(Iop_32to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_16HLto32, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel
{ DEFOP(Iop_64to32, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_64HIto32, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
@@ -151,15 +151,15 @@
{ DEFOP(Iop_128HIto64, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_Not1, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_64to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
- { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_1Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_1Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
- { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_1Sto16, UNDEF_ALL), }, // not handled by mc_translate
- { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
- { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_AddF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_SubF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
@@ -178,11 +178,11 @@
{ DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
- { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
{ DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
Modified: trunk/none/tests/mips32/Makefile.am
==============================================================================
--- trunk/none/tests/mips32/Makefile.am (original)
+++ trunk/none/tests/mips32/Makefile.am Wed Oct 23 14:07:15 2013
@@ -24,7 +24,7 @@
SignalException.stderr.exp SignalException.vgtest \
bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
bug320057-mips32.vgtest \
- mips32_dsp.stdout.exp mips32_dsp.stdout.exp-BE \
+ mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
mips32_dsp.stderr.exp mips32_dsp.vgtest \
mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
mips32_dspr2.vgtest \
Modified: trunk/none/tests/mips32/mips32_dsp.c
==============================================================================
--- trunk/none/tests/mips32/mips32_dsp.c (original)
+++ trunk/none/tests/mips32/mips32_dsp.c Wed Oct 23 14:07:15 2013
@@ -566,14 +566,14 @@
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0x0555adec, t2, t3);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0x980b7cde, t4, t1);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0xf973437b, t6, t7);
- TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x93474bde, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x23c54b6e, t5, t3);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0x55555555, t2, t4);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xc4dbfe20, t0, t8);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0x734680bc, t4, t4);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x00354565, t0, t1);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0xbacabaca, t2, t3);
- TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xdecadeca, t4, t1);
- TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x00000286, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xdba38ec9, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x0b300286, t6, t7);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0xabababab, t5, t3);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0x00086755, t2, t4);
TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0x8f8f8f80, t0, t8);
@@ -612,14 +612,14 @@
TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0x0555adec, t2, t3);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0x980b7cde, t4, t1);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0xf973437b, t6, t7);
- TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x93474bde, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x23c54b6e, t5, t3);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0x55555555, t2, t4);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xc4dbfe20, t0, t8);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0x734680bc, t4, t4);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x00354565, t0, t1);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0xbacabaca, t2, t3);
- TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xdecadeca, t4, t1);
- TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x00000286, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xdba38ec9, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x0b300286, t6, t7);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0xabababab, t5, t3);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0x00086755, t2, t4);
TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0x8f8f8f80, t0, t8);
@@ -656,11 +656,11 @@
t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0xf973437b, 0x80000000,
t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xfa3259ff,
t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff,
t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0034c420, 0x00000555,
t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x00000004, 1073741824,
t2, t3, t4);
@@ -668,7 +668,7 @@
t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0x76548000, 0x73468000,
t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0x80000000, 0x80000000,
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0x80000000, 0x80620020,
t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
t2, t4, t8);
@@ -676,7 +676,7 @@
t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x000a2300, 0x83bc1900,
t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x80000000, 0x80000000,
t2, t3, t4);
@@ -727,494 +727,504 @@
printf("-------- ADDQ_S.PH --------\n");
TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00045fb2, 0x00000286,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x00002435, 0xffff3421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xf973437b, 0x80000000,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00000004, 1073741824,
- t2, t3, t4);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x80002435, 0x80003421,
- t4, t1, t5);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x76548000, 0x73468000,
- t6, t7, t3);
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00010001, 0xfa3259ff,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x7fff7322, 0x77ff7fff,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x0034c420, 0x00000555,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x00000004, 1073741824,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x80002435, 0x80003421,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x76548000, 0x73468000,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x80000000, 0x80620020,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x00010001, 0xffffffff,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x7fff7fff, 0x7fff7fff,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x0000c420, 0x00000555,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x000a2300, 0x83bc1900,
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x80000000, 0x80000000,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x80000000, 0x80000000,
- t2, t3, t4);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
- t4, t1, t5);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x00000018, 0xffff2435,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xaaaaaaaa, 0x55555555,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x00000018, 0xffff2435,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbabababa, 0xabababab,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0xf0f0f0f0, 0xfc79b4d2,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0xfbde3976, 0x00000000,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x23534870, 0x00354565,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x980b7cde, 0x00086755,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x00000018, 0x8f8f8f8f,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x92784656, 0xeeeeeeee,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xcacacaca, 0x1bdbdbdb,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbacabaca, 0xdecadeca,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x12fadeb4, 0x93474bde,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x7c000790, 0xfc0007ff,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xffffffff, 0xffffffff,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0xf2f4df1f, 0xcb4ab48f,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x435f909a, 0xaf8f7e18,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x2106ba5f, 0x87df4510,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x246a6376, 0xabf4e8e1,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x1046a1a3, 0xf4c0eeac,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x638ca515, 0x006a54f2,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0xf63e7a9d, 0x79f74493,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xbd6845cd, 0x9c09e313,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x234ba291, 0xbb64981c,
t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xbabababa, 0xabababab,
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x120934de, 0xad2c7601,
t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xf5643908, 0xbaff3492,
t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xfbde3976, 0x00000000,
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x88503331, 0xd60e34a2,
t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x23534870, 0x00354565,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x980b7cde, 0x00086755,
- t0, t1, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
- t2, t3, t4);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
- t4, t1, t5);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
- t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xffffffff, 0xffffffff,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
- t0, t1, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
- t2, t3, t4);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
- t4, t1, t5);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
- t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313,
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x7b5309ac, 0xc5487201,
t4, t6, t1);
printf("-------- ADDQ_S.W --------\n");
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00045fb2, 0x00000286,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x00002435, 0xffff3421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xf973437b, 0x80000000,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xfa3259ff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0034c420, 0x00000555,
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00000004, 1073741824,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x80002435, 0x80003421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x76548000, 0x73468000,
- t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x80000000, 0x80000000,
- t5, t3, t2);
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x80000000, 0x80620020,
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x000a2300, 0x83bc1900,
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x80000000, 0x80000000,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x00000018, 0xffff2435,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xbabababa, 0xabababab,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0xfbde3976, 0x00000000,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x23534870, 0x00354565,
- t4, t6, t1);
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x980b7cde, 0x00086755,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0xffffffff, 0xffffffff,
- t4, t6, t1);
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313,
t4, t6, t1);
printf("-------- ADDSC --------\n");
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00045fb2, 0x00000286,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x00002435, 0xffff3421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xf973437b, 0x80000000,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xfa3259ff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0034c420, 0x00000555,
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00000004, 1073741824,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x80002435, 0x80003421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x76548000, 0x73468000,
- t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x80000000, 0x80000000,
- t5, t3, t2);
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x80000000, 0x80620020,
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x000a2300, 0x83bc1900,
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x80000000, 0x80000000,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x00000018, 0xffff2435,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xbabababa, 0xabababab,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0xfbde3976, 0x00000000,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x23534870, 0x00354565,
- t4, t6, t1);
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x980b7cde, 0x00086755,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0xffffffff, 0xffffffff,
- t4, t6, t1);
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313,
t4, t6, t1);
printf("-------- ADDU.QB --------\n");
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x00045fb2, 0x00000286,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x00002435, 0xffff3421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0xf973437b, 0x80000000,
- t5, t3, t2);
- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x00010001, 0xfa3259ff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x0034c420, 0x00000555,
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x00000004, 1073741824,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x80002435, 0x80003421,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x76548000, 0x73468000,
- t6, t7, t3);
- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0x80000000, 0x80000000,
- t5, t3, t2);
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0x80000000, 0x80620020,
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x00010001, 0xffffffff,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x0000c420, 0x00000555,
- t4, t6, t1);
- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x00000000, 0x00000000,
- t0, t1, t2);
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x000a2300, 0x83bc1900,
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x80000000, 0x80000000,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x00000018, 0xffff2435,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0xbabababa, 0xabababab,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0xfbde3976, 0x00000000,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x23534870, 0x00354565,
- t4, t6, t1);
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x980b7cde, 0x00086755,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
- t2, t4, t8);
+ t2, t4, t8);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
- t0, t8, t0);
+ t0, t8, t0);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0xffffffff, 0xffffffff,
- t4, t6, t1);
+ t4, t6, t1);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
- t0, t1, t2);
+ t0, t1, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
- t2, t3, t4);
+ t2, t3, t4);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
- t4, t1, t5);
+ t4, t1, t5);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
- t6, t7, t3);
+ t6, t7, t3);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
- t5, t3, t2);
+ t5, t3, t2);
TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
- t2, t4, t8);
+ t2, t4, t8...
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