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From: <sv...@va...> - 2013-10-07 10:29:06
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Author: dejanj
Date: Mon Oct 7 10:28:56 2013
New Revision: 2783
Log:
mips64: add extra Iop cases in VEX.
Modified:
trunk/priv/host_mips_defs.c
trunk/priv/host_mips_defs.h
trunk/priv/host_mips_isel.c
Modified: trunk/priv/host_mips_defs.c
==============================================================================
--- trunk/priv/host_mips_defs.c (original)
+++ trunk/priv/host_mips_defs.c Mon Oct 7 10:28:56 2013
@@ -3960,6 +3960,11 @@
fr_src = dregNo(i->Min.FpConvert.src);
p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0F);
break;
+ case Mfp_FLOORLD:
+ fr_dst = dregNo(i->Min.FpConvert.dst);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0B);
+ break;
default:
goto bad;
Modified: trunk/priv/host_mips_defs.h
==============================================================================
--- trunk/priv/host_mips_defs.h (original)
+++ trunk/priv/host_mips_defs.h Mon Oct 7 10:28:56 2013
@@ -367,7 +367,7 @@
Mfp_CVTWS, Mfp_CVTDL, Mfp_CVTSL, Mfp_CVTLS, Mfp_CVTLD, Mfp_TRULS, Mfp_TRULD,
Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS, Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD,
Mfp_CVTDW, Mfp_CMP, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD,
- Mfp_CVTDS, Mfp_ROUNDLD
+ Mfp_CVTDS, Mfp_ROUNDLD, Mfp_FLOORLD
} MIPSFpOp;
Modified: trunk/priv/host_mips_isel.c
==============================================================================
--- trunk/priv/host_mips_isel.c (original)
+++ trunk/priv/host_mips_isel.c Mon Oct 7 10:28:56 2013
@@ -836,6 +836,8 @@
aluOp = Malu_DSUB;
break;
+ case Iop_And8:
+ case Iop_And16:
case Iop_And32:
case Iop_And64:
aluOp = Malu_AND;
@@ -848,6 +850,8 @@
aluOp = Malu_OR;
break;
+ case Iop_Xor8:
+ case Iop_Xor16:
case Iop_Xor32:
case Iop_Xor64:
aluOp = Malu_XOR;
@@ -1364,6 +1368,7 @@
case Iop_1Sto8:
case Iop_1Sto16:
case Iop_1Sto32:
+ case Iop_8Sto16:
case Iop_8Sto32:
case Iop_16Sto32:
case Iop_16Sto64:
@@ -1394,6 +1399,10 @@
amt = 48;
sz32 = False;
break;
+ case Iop_8Sto16:
+ amt = 24;
+ sz32 = True;
+ break;
case Iop_8Sto32:
amt = 24;
sz32 = True;
@@ -1484,11 +1493,10 @@
}
case Iop_16to8:
+ case Iop_32to1:
case Iop_32to8:
case Iop_32to16:
return iselWordExpr_R(env, e->Iex.Unop.arg);
- case Iop_32to1:
- return iselWordExpr_R(env, e->Iex.Unop.arg);
case Iop_32HIto16: {
HReg r_dst = newVRegI(env);
@@ -1498,13 +1506,15 @@
return r_dst;
}
+ case Iop_64to1:
case Iop_64to8: {
vassert(mode64);
HReg r_src, r_dst;
+ UShort mask = (op_unop == Iop_64to1) ? 0x1 : 0xFF;
r_dst = newVRegI(env);
r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
- MIPSRH_Imm(False, 0xFF)));
+ MIPSRH_Imm(False, mask)));
return r_dst;
}
@@ -1516,6 +1526,7 @@
return r_dst;
}
+ case Iop_1Uto8:
case Iop_1Uto32:
case Iop_1Uto64:
case Iop_8Uto16:
@@ -1529,6 +1540,7 @@
switch (op_unop) {
case Iop_1Uto64:
vassert(mode64);
+ case Iop_1Uto8:
case Iop_1Uto32:
mask = toUShort(0x1);
break;
@@ -2201,22 +2213,21 @@
switch (e->Iex.Binop.op) {
/* 64 x 64 -> 128 multiply */
case Iop_MullU64:
- case Iop_MullS64:
- {
- HReg tLo = newVRegI(env);
- HReg tHi = newVRegI(env);
- Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
- addInstr(env, MIPSInstr_Mul(syned, True, False /*64bit mul */ ,
- r_dst, r_srcL, r_srcR));
- addInstr(env, MIPSInstr_Mfhi(tHi));
- addInstr(env, MIPSInstr_Mflo(tLo));
- *rHi = tHi;
- *rLo = tLo;
- return;
- }
+ case Iop_MullS64: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, MIPSInstr_Mul(syned, True, False /*64bit mul */ ,
+ r_dst, r_srcL, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
/* 64HLto128(e1,e2) */
case Iop_64HLto128:
@@ -2239,7 +2250,8 @@
return;
}
- case Iop_DivModU128to64: {
+ case Iop_DivModU128to64:
+ case Iop_DivModS128to64: {
vassert(mode64);
HReg rHi1, rLo1;
iselInt128Expr(&rHi1, &rLo1, env, e->Iex.Binop.arg1);
@@ -2952,6 +2964,28 @@
addInstr(env, MIPSInstr_FpConvert(Mfp_TRULD, dst, src));
return dst;
}
+ case Iop_RoundF64toF64_NEAREST: {
+ vassert(mode64);
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegF(env);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_ROUNDLD, dst, src));
+ return dst;
+ }
+ case Iop_RoundF64toF64_NegINF: {
+ vassert(mode64);
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegF(env);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_FLOORLD, dst, src));
+ return dst;
+ }
+ case Iop_RoundF64toF64_PosINF: {
+ vassert(mode64);
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegF(env);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CEILLD, dst, src));
+ return dst;
+ }
+
default:
break;
}
@@ -3349,7 +3383,7 @@
return valD1;
}
- case Iop_SqrtF64:{
+ case Iop_SqrtF64: {
/* first arg is rounding mode; we ignore it. */
HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
HReg dst = newVRegD(env);
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