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From: <sv...@va...> - 2013-09-27 15:04:13
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Author: sewardj
Date: Fri Sep 27 15:03:58 2013
New Revision: 2776
Log:
Add a kludgey implementation of XTEST to go with the kludgey
implementation of XBEGIN. Also kludge the CPUID output for AVX
capable targets so as to claim we support HTM.
Mark Wielaard, mj...@re...)
Modified:
trunk/priv/guest_amd64_helpers.c
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_helpers.c
==============================================================================
--- trunk/priv/guest_amd64_helpers.c (original)
+++ trunk/priv/guest_amd64_helpers.c Fri Sep 27 15:03:58 2013
@@ -2570,7 +2570,7 @@
/* Claim to be the following CPU (4 x ...), which is AVX and cx16
- capable.
+ capable. Plus (kludge!) it "supports" HTM.
vendor_id : GenuineIntel
cpu family : 6
@@ -2651,7 +2651,7 @@
SET_ABCD(0x00000077, 0x00000002, 0x00000009, 0x00000000);
break;
case 0x00000007:
- SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ SET_ABCD(0x00000000, 0x00000800, 0x00000000, 0x00000000);
break;
case 0x00000008:
SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Fri Sep 27 15:03:58 2013
@@ -20066,8 +20066,8 @@
return delta;
}
/* BEGIN HACKY SUPPORT FOR xbegin */
- if (0/*CURRENTLY DISABLED*/ &&
- modrm == 0xF8 && !haveF2orF3(pfx) && sz == 4) {
+ if (modrm == 0xF8 && !have66orF2orF3(pfx) && sz == 4
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
delta++; /* mod/rm byte */
d64 = getSDisp(4,delta);
delta += 4;
@@ -20723,6 +20723,22 @@
putIRegRDX(4, mkU32(0));
return delta;
}
+ /* BEGIN HACKY SUPPORT FOR xtest */
+ /* 0F 01 D6 = XTEST */
+ if (modrm == 0xD6 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
+ /* Sets ZF because there never is a transaction, and all
+ CF, OF, SF, PF and AF are always cleared by xtest. */
+ delta += 1;
+ DIP("xtest\n");
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkU64(AMD64G_CC_MASK_Z) ));
+ /* Set NDEP even though it isn't used. This makes redundant-PUT
+ elimination of previous stores to this field work better. */
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ return delta;
+ }
+ /* END HACKY SUPPORT FOR xtest */
/* 0F 01 F9 = RDTSCP */
if (modrm == 0xF9 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_RDTSCP)) {
delta += 1;
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