|
From: <sv...@va...> - 2013-08-09 21:55:59
|
carll 2013-08-09 22:55:45 +0100 (Fri, 09 Aug 2013)
New Revision: 13490
Log:
The following instructions were introduced in the Power ISA 2.05
(i.e., POWER6) - lfdp - stfdp - lfdpx - stfdpx These instructions were promptly
deprecated (phased out) in ISA 2.06 (i.e., POWER7). Recent updates in binutils
no longer supports these instructions unless the assembler is invoked with
'-mpower6'. When 'make check' is run on valgrind when using such a newer
binutils and running on a ppc64 system newer than POWER6, you get the
following build error:
y
pc64_linux=1 -DVGPV_ppc64_linux_vanilla=1 -DVGA_SEC_ppc32=1 -DVGP_SEC_ppc64_linux=1 -Winline -Wall -Wshadow -g -Winline -Wall -Wshadow -g -I../../../include -m64 -Wno-long-long -Wwrite-strings -fno-stack-protector -Wno-write-strings -MT power_ISA2_05-power_ISA2_05.o -MD -MP -MF .deps/power_ISA2_05-power_ISA2_05.Tpo -c -o power_ISA2_05-power_ISA2_05.o `test -f 'power_ISA2_05.c' || echo './'`power_ISA2_05.c
/tmp/cciGIkGG.s:Assembler messages:
/tmp/cciGIkGG.s:387: Error: operand out of domain (31 is not a multiple of 4)
/tmp/cciGIkGG.s:387: Error: syntax error; found `,', expected `('
/tmp/cciGIkGG.s:387: Error: junk at end of line: `,9'
/tmp/cciGIkGG.s:478: Error: operand out of domain (31 is not a multiple of 4)
/tmp/cciGIkGG.s:478: Error: syntax error; found `,', expected `('
/tmp/cciGIkGG.s:478: Error: junk at end of line: `,9'
make[2]: *** [power_ISA2_05-power_ISA2_05.o] Error 1
make[2]: Leaving directory `/tmp/Valgrind_review/valgrind_ISA2_05/memcheck/tests/ppc64'
make[1]: *** [check-am] Error 2
make[1]: Leaving directory `/tmp/Valgrind_review/valgrind_ISA2_05/memcheck/tests/ppc64' make: *** [check-recursive] Error 1
This patch fixes the problem by adding a configure check to determine if these
phased out instructions are supported by the binutils, and the result of that
configure check is used to decide whether or not to compile in the source for
testing these instructions.
Bugzilla 323116
committed by Carl Love, ca...@us...
Added files:
trunk/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO
trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO
Modified files:
trunk/configure.in
trunk/memcheck/tests/ppc32/Makefile.am
trunk/memcheck/tests/ppc32/power_ISA2_05.c
trunk/memcheck/tests/ppc64/Makefile.am
trunk/memcheck/tests/ppc64/power_ISA2_05.c
Modified: trunk/memcheck/tests/ppc32/Makefile.am (+2 -1)
===================================================================
--- trunk/memcheck/tests/ppc32/Makefile.am 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/memcheck/tests/ppc32/Makefile.am 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -4,7 +4,8 @@
dist_noinst_SCRIPTS = filter_stderr
EXTRA_DIST = $(noinst_SCRIPTS) \
- power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest
+ power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
+ power_ISA2_05.stdout.exp_Without_FPPO
check_PROGRAMS = \
power_ISA2_05
Modified: trunk/memcheck/tests/ppc64/Makefile.am (+2 -1)
===================================================================
--- trunk/memcheck/tests/ppc64/Makefile.am 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/memcheck/tests/ppc64/Makefile.am 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -4,7 +4,8 @@
dist_noinst_SCRIPTS = filter_stderr
EXTRA_DIST = $(noinst_SCRIPTS) \
- power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest
+ power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
+ power_ISA2_05.stdout.exp_Without_FPPO
check_PROGRAMS = \
power_ISA2_05
Modified: trunk/memcheck/tests/ppc64/power_ISA2_05.c (+9 -0)
===================================================================
--- trunk/memcheck/tests/ppc64/power_ISA2_05.c 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/memcheck/tests/ppc64/power_ISA2_05.c 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -1,4 +1,5 @@
#include <stdio.h>
+#include <config.h>
double foo = -1.0;
double FRT1;
@@ -63,9 +64,16 @@
** FPp = leftmost 64 bits stored at DS(RA)
** FPp+1= rightmost 64 bits stored at DS(RA)
** FPp must be an even float register
+**
+** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out"
+** category in ISA 2.06 (i.e., POWER7 timeframe). If valgrind and its
+** testsuite are built with -mcpu=power7 (or later), then the assembler will
+** not recognize those phased out instructions.
+**
*/
void test_double_pair_instrs()
{
+#ifdef HAVE_AS_PPC_FPPO
typedef struct {
double hi;
double lo;
@@ -120,6 +128,7 @@
__asm__ volatile ("stfdpx 10, 20, 21");
printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
+#endif
}
Modified: trunk/configure.in (+22 -0)
===================================================================
--- trunk/configure.in 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/configure.in 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -1771,6 +1771,28 @@
fi
+# does the ppc assembler support "lfdp" and other phased out floating point insns?
+AC_MSG_CHECKING([if ppc32/64 asm supports phased out floating point instructions])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do { typedef struct {
+ double hi;
+ double lo;
+ } dbl_pair_t;
+ dbl_pair_t dbl_pair[3];
+ __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
+ } while (0)
+]])], [
+ac_have_as_ppc_fpPO=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_ppc_fpPO=no
+AC_MSG_RESULT([no])
+])
+if test x$ac_have_as_ppc_fpPO = xyes ; then
+ AC_DEFINE(HAVE_AS_PPC_FPPO, 1, [Define to 1 if as supports floating point phased out category.])
+fi
+
CFLAGS=$safe_CFLAGS
# does the x86/amd64 assembler understand SSE3 instructions?
Added: trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO (+119 -0)
===================================================================
--- trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -0,0 +1,119 @@
+lwarx => 0
+ldarx => bad0beef
+fcpsgn sign=10.101010, base=11.111111 => 11.111111
+fcpsgn sign=10.101010, base=-0.000000 => 0.000000
+fcpsgn sign=10.101010, base=0.000000 => 0.000000
+fcpsgn sign=10.101010, base=-11.111111 => 11.111111
+fcpsgn sign=-0.000000, base=11.111111 => -11.111111
+fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
+fcpsgn sign=-0.000000, base=0.000000 => -0.000000
+fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
+fcpsgn sign=0.000000, base=11.111111 => 11.111111
+fcpsgn sign=0.000000, base=-0.000000 => 0.000000
+fcpsgn sign=0.000000, base=0.000000 => 0.000000
+fcpsgn sign=0.000000, base=-11.111111 => 11.111111
+fcpsgn sign=-10.101010, base=11.111111 => -11.111111
+fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
+fcpsgn sign=-10.101010, base=0.000000 => -0.000000
+fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
+lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
+prtyd (0) => parity=0
+prtyw (0) => parity=0
+prtyd (1) => parity=1
+prtyw (1) => parity=1
+prtyd (2) => parity=0
+prtyw (2) => parity=0
+prtyd (3) => parity=1
+prtyw (3) => parity=1
+prtyd (4) => parity=0
+prtyw (4) => parity=0
+prtyd (5) => parity=1
+prtyw (5) => parity=1
+prtyd (6) => parity=0
+prtyw (6) => parity=0
+prtyd (7) => parity=1
+prtyw (7) => parity=1
+prtyd (8) => parity=0
+prtyw (8) => parity=0
+prtyd (9) => parity=1
+prtyw (9) => parity=1
+prtyd (a) => parity=0
+prtyw (a) => parity=0
+prtyd (b) => parity=1
+prtyw (b) => parity=1
+prtyd (c) => parity=0
+prtyw (c) => parity=0
+prtyd (d) => parity=1
+prtyw (d) => parity=1
+prtyd (e) => parity=0
+prtyw (e) => parity=0
+prtyd (f) => parity=1
+prtyw (f) => parity=1
+prtyd (10) => parity=0
+prtyw (10) => parity=0
+prtyd (11) => parity=1
+prtyw (11) => parity=1
+prtyd (12) => parity=0
+prtyw (12) => parity=0
+prtyd (13) => parity=1
+prtyw (13) => parity=1
+prtyd (14) => parity=0
+prtyw (14) => parity=0
+prtyd (15) => parity=1
+prtyw (15) => parity=1
+prtyd (16) => parity=0
+prtyw (16) => parity=0
+prtyd (17) => parity=1
+prtyw (17) => parity=1
+prtyd (18) => parity=0
+prtyw (18) => parity=0
+prtyd (19) => parity=1
+prtyw (19) => parity=1
+prtyd (1a) => parity=0
+prtyw (1a) => parity=0
+prtyd (1b) => parity=1
+prtyw (1b) => parity=1
+prtyd (1c) => parity=0
+prtyw (1c) => parity=0
+prtyd (1d) => parity=1
+prtyw (1d) => parity=1
+prtyd (1e) => parity=0
+prtyw (1e) => parity=0
+prtyd (1f) => parity=1
+prtyw (1f) => parity=1
+prtyd (20) => parity=0
+prtyw (20) => parity=0
+prtyd (21) => parity=1
+prtyw (21) => parity=1
+prtyd (22) => parity=0
+prtyw (22) => parity=0
+prtyd (23) => parity=1
+prtyw (23) => parity=1
+prtyd (24) => parity=0
+prtyw (24) => parity=0
+prtyd (25) => parity=1
+prtyw (25) => parity=1
+prtyd (26) => parity=0
+prtyw (26) => parity=0
+prtyd (27) => parity=1
+prtyw (27) => parity=1
+prtyd (28) => parity=0
+prtyw (28) => parity=0
+prtyd (29) => parity=1
+prtyw (29) => parity=1
+prtyd (2a) => parity=0
+prtyw (2a) => parity=0
+prtyd (2b) => parity=1
+prtyw (2b) => parity=1
+prtyd (2c) => parity=0
+prtyw (2c) => parity=0
+prtyd (2d) => parity=1
+prtyw (2d) => parity=1
+prtyd (2e) => parity=0
+prtyw (2e) => parity=0
+prtyd (2f) => parity=1
+prtyw (2f) => parity=1
+prtyd (30) => parity=0
+prtyw (30) => parity=0
+prtyd (31) => parity=1
+prtyw (31) => parity=1
Property changed: trunk/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO (+0 -0)
___________________________________________________________________
Name: svn:special
+ *
Added: trunk/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO (+1 -0)
===================================================================
--- trunk/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -0,0 +1 @@
+link ../ppc64/power_ISA2_05.stdout.exp_Without_FPPO
\ No newline at end of file
Modified: trunk/memcheck/tests/ppc32/power_ISA2_05.c (+8 -0)
===================================================================
--- trunk/memcheck/tests/ppc32/power_ISA2_05.c 2013-08-08 11:56:08 +01:00 (rev 13489)
+++ trunk/memcheck/tests/ppc32/power_ISA2_05.c 2013-08-09 22:55:45 +01:00 (rev 13490)
@@ -1,4 +1,5 @@
#include <stdio.h>
+#include <config.h>
double foo = -1.0;
double FRT1;
@@ -65,9 +66,15 @@
** FPp = leftmost 64 bits stored at DS(RA)
** FPp+1= rightmost 64 bits stored at DS(RA)
** FPp must be an even float register
+**
+** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out"
+** category in ISA 2.06 (i.e., POWER7 timeframe). If valgrind and its
+** testsuite are built with -mcpu=power7 (or later), then the assembler will
+** not recognize those phased out instructions.
*/
void test_double_pair_instrs()
{
+#ifdef HAVE_AS_PPC_FPPO
typedef struct {
double hi;
double lo;
@@ -122,6 +129,7 @@
__asm__ volatile ("stfdpx 10, 20, 21");
printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
+#endif
}
|