|
From: <sv...@va...> - 2013-08-02 15:40:14
|
dejanj 2013-08-02 16:39:58 +0100 (Fri, 02 Aug 2013)
New Revision: 13479
Log:
mips32: Add test cases for for mips32 DSP instruction set.
Add test cases for mips32 DSP and DSP revision 2 ASE.
Correctly model SHLL_S.PH on MIPS32.
Added files:
trunk/none/tests/mips32/mips32_dsp.c
trunk/none/tests/mips32/mips32_dsp.stderr.exp
trunk/none/tests/mips32/mips32_dsp.stdout.exp
trunk/none/tests/mips32/mips32_dsp.stdout.exp-BE
trunk/none/tests/mips32/mips32_dsp.vgtest
trunk/none/tests/mips32/mips32_dspr2.c
trunk/none/tests/mips32/mips32_dspr2.stderr.exp
trunk/none/tests/mips32/mips32_dspr2.stdout.exp
trunk/none/tests/mips32/mips32_dspr2.vgtest
trunk/tests/mips32_features.c
Modified files:
trunk/none/tests/mips32/Makefile.am
trunk/tests/Makefile.am
Added: trunk/none/tests/mips32/mips32_dsp.vgtest (+3 -0)
===================================================================
--- trunk/none/tests/mips32/mips32_dsp.vgtest 2013-08-01 23:16:41 +01:00 (rev 13478)
+++ trunk/none/tests/mips32/mips32_dsp.vgtest 2013-08-02 16:39:58 +01:00 (rev 13479)
@@ -0,0 +1,3 @@
+prog: mips32_dsp
+prereq: ../../../tests/mips32_features mips32-dsp
+vgopts: -q
Added: trunk/none/tests/mips32/mips32_dsp.c (+7429 -0)
===================================================================
--- trunk/none/tests/mips32/mips32_dsp.c 2013-08-01 23:16:41 +01:00 (rev 13478)
+++ trunk/none/tests/mips32/mips32_dsp.c 2013-08-02 16:39:58 +01:00 (rev 13479)
@@ -0,0 +1,7429 @@
+#include <stdio.h>
+/* Independent tests for each DSP instruction from MIPS32 DSP ASE instruction
+ set */
+
+unsigned int mem[] = {
+ 0x121f1e1f, 0, 3, -1,
+ 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a,
+ 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a,
+ 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+};
+
+void ppMem(unsigned int* _mem, int _len)
+{
+ int i;
+ printf("MEM:\n");
+ for (i = 0; i < _len; i=i+4)
+ {
+ printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ _mem[i], _mem[i+1], _mem[i+2], _mem[i+3]);
+ }
+ _mem[0] = 0x121f1e1f;
+ _mem[1] = 0;
+ _mem[2] = 3;
+ _mem[3] = -1;
+ _mem[4] = 0x232f2e2f;
+ _mem[5] = 0x242c2b2b;
+ _mem[6] = 0x252a2e2b;
+ _mem[7] = 0x262d2d2a;
+ _mem[8] = 0x3f343f3e;
+ _mem[9] = 0x3e353d3c;
+ _mem[10] = 0x363a3c3b;
+ _mem[11] = 0x3b373b3a;
+ _mem[12] = 0x454f4e45;
+ _mem[13] = 0x4e464d46;
+ _mem[14] = 0x474d474c;
+ _mem[15] = 0x4a484a4c;
+}
+
+#define TESTDSPINST_RD_RT_DSPC(instruction, RTval, RD, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ "wrdsp $zero, 0x3f \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ "rddsp %1, 0x3f \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl) \
+ : "r" (RTval) \
+ : #RT, #RD \
+ ); \
+ printf("%s :: rd 0x%08x rt 0x%08x DSPControl 0x%x\n", \
+ instruction, out, RTval, dspCtrl); \
+}
+
+#define TESTDSPINST_RD_RT_NODSPC(instruction, RTval, RD, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "move $" #RT ", %1 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : "r" (RTval) \
+ : #RT, #RD \
+ ); \
+ printf("%s :: rd 0x%08x rt 0x%08x \n", \
+ instruction, out, RTval); \
+}
+
+#define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "wrdsp $zero, 0x3f \n\t" \
+ "move $" #RS ", %2 \n\t" \
+ "move $" #RT ", %3 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ "rddsp %1, 0x3f \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl) \
+ : "r" (RSval), "r"(RTval) \
+ : #RD, #RS, #RT \
+ ); \
+ printf("%s :: rs 0x%08x rt 0x%08x out 0x%08x DSPCtrl 0x%08x\n", \
+ instruction, RSval, RTval, out, dspCtrl); \
+}
+
+#define TESTDSPINST_BPOSGE32(instruction, RDval, POSval, RD, POSreg) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #POSreg ", %1 \n\t" \
+ "wrdsp $" #POSreg ", 0x3f \n\t" \
+ "move $" #RD ", %2 \n\t" \
+ instruction" end"instruction#RDval" \n\t" \
+ "nop \n\t" \
+ "addi $" #RD ", $" #RD", 5 \n\t" \
+ "end"instruction#RDval": \n\t" \
+ "addi $" #RD ", $" #RD", 1 \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : "r" (POSval), "r" (RDval) \
+ : #RD, #POSreg \
+ ); \
+ printf(instruction" :: %d, POSval: %d\n", \
+ out, POSval); \
+}
+
+#define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \
+{ \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "wrdsp $zero, 0x3f \n\t" \
+ "move $" #RS ", %1 \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ instruction " \n\t" \
+ "rddsp %0, 0x3f \n\t" \
+ : "=&r" (dspCtrl) \
+ : "r" (RSval), "r"(RTval) \
+ : #RS, #RT \
+ ); \
+ printf("%s :: rs 0x%08x rt 0x%08x DSPCtrl 0x%08x \n", \
+ instruction, RSval, RTval, dspCtrl); \
+}
+
+#define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "move $" #RS ", %1 \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r"(RTval) \
+ : #RD, #RS, #RT \
+ ); \
+ printf("%s :: rs 0x%08x rt 0x%08x out 0x%08x\n", \
+ instruction, RSval, RTval, out); \
+}
+
+#define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \
+ RS, RT) \
+{ \
+ int out_hi = 0xdeadbeef; \
+ int out_lo = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %5 \n\t" \
+ "move $" #RT ", %6 \n\t" \
+ "mthi $" #RS", $" ac " \n\t" \
+ "mtlo $" #RT", $" ac " \n\t" \
+ "move $" #RS ", %3 \n\t" \
+ "move $" #RT ", %4 \n\t" \
+ "wrdsp $zero, 0x3f \n\t" \
+ instruction " \n\t" \
+ "rddsp %2, 0x3f \n\t" \
+ "mfhi %0, $" ac " \n\t" \
+ "mflo %1, $" ac " \n\t" \
+ : "=&r" (out_hi), "=&r" (out_lo), "=&r" (dspCtrl) \
+ : "r" (RSval), "r"(RTval), "r" (HIval), "r"(LOval) \
+ : #RS, #RT \
+ ); \
+ printf("%s :: rs 0x%08x rt 0x%08x inHI 0x%08x inLO 0x%08x outHI 0x%08x outLO\
+ 0x%08x dspCtrl 0x%08x\n",instruction, RSval, RTval, HIval, LOval, \
+ out_hi, out_lo, dspCtrl); \
+}
+
+#define TESTDSPINST_AC_RS_RT_NODSPC(instruction, ac, RSval, RTval, HIval, \
+ LOval, RS, RT) \
+{ \
+ int out_hi = 0xdeadbeef; \
+ int out_lo = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %4 \n\t" \
+ "move $" #RT ", %5 \n\t" \
+ "mthi $" #RS", $" ac " \n\t" \
+ "mtlo $" #RT", $" ac " \n\t" \
+ "move $" #RS ", %2 \n\t" \
+ "move $" #RT ", %3 \n\t" \
+ instruction " \n\t" \
+ "mfhi %0, $" ac " \n\t" \
+ "mflo %1, $" ac " \n\t" \
+ : "=&r" (out_hi), "=&r" (out_lo) \
+ : "r" (RSval), "r"(RTval), "r" (HIval), "r"(LOval) \
+ : #RS, #RT \
+ ); \
+ printf("%s :: rs 0x%08x rt 0x%08x inHI 0x%08x inLO 0x%08x outHI 0x%08x outLO\
+ 0x%08x \n",instruction, RSval, RTval, HIval, LOval, out_hi, out_lo); \
+}
+
+#define TESTDSPINST_EXT(instruction, ac, RT, HIval, LOval, size, pos) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ "wrdsp $" #RT ", 0x3f \n\t" \
+ "move $" #RT ", %3 \n\t" \
+ "mthi $" #RT", $" ac " \n\t" \
+ "move $" #RT ", %4 \n\t" \
+ "mtlo $" #RT", $" ac " \n\t" \
+ instruction " \n\t" \
+ "rddsp %1, 0x3f \n\t" \
+ "move %0, $" #RT " \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl) \
+ : "r" (pos), "r" (HIval), "r" (LOval) \
+ : #RT \
+ ); \
+ printf("%s :: rt 0x%08x %s 0x%08x%08x size %2d DSPCtrl 0x%08x\n", \
+ instruction, out, ac, HIval, LOval, size, dspCtrl); \
+}
+
+#define TESTDSPINST_EXTV(instruction, ac, RT, HIval, LOval, RS, RSval, pos) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %5 \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ "wrdsp $" #RT ", 0x3f \n\t" \
+ "move $" #RT ", %3 \n\t" \
+ "mthi $" #RT", $" ac " \n\t" \
+ "move $" #RT ", %4 \n\t" \
+ "mtlo $" #RT", $" ac " \n\t" \
+ instruction " \n\t" \
+ "rddsp %1, 0x3f \n\t" \
+ "move %0, $" #RT " \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl) \
+ : "r" (pos), "r" (HIval), "r" (LOval), "r" (RSval) \
+ : #RT, #RS \
+ ); \
+ printf("%s :: rt 0x%08x %s 0x%08x%08x rs 0x%08x DSPCtrl 0x%08x\n", \
+ instruction, out, ac, HIval, LOval, RSval, dspCtrl); \
+}
+
+#define TESTDSPINST_INSV(instruction, RTval, RSval, RT, RS, _pos, _size) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %3 \n\t" \
+ "wrdsp $" #RS ", 0x1 \n\t" \
+ "move $" #RS ", %4 \n\t" \
+ "wrdsp $" #RS ", 0x2 \n\t" \
+ "move $" #RS", %1 \n\t" \
+ "move $" #RT", %2 \n\t" \
+ "insv $" #RT ", $" #RS " \n\t" \
+ "move %0, $" #RT " \n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RTval), "r" (_pos), "r" (_size) \
+ : #RS, #RT \
+ ); \
+ printf("insv :: out: 0x%08x rtIN 0x%08x rsIN 0x%08x posI %2d sizeI %2d \n", \
+ out, RTval, RSval, _pos, _size>>7); \
+}
+
+#define TESTDSPINST_LWX(index, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS", %1 \n\t" \
+ "move $" #RT", %2 \n\t" \
+ "lwx %0, $" #RT "($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (index) \
+ : #RT, #RS, "memory" \
+ ); \
+ printf("lwx :: out: 0x%08x mem[%d]\n", out, index); \
+}
+
+#define TESTDSPINST_LHX(index, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS", %1 \n\t" \
+ "move $" #RT", %2 \n\t" \
+ "lhx %0, $" #RT "($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (index) \
+ : #RT, #RS, "memory" \
+ ); \
+ printf("lhx :: out: 0x%08x mem[%d]\n", out, index); \
+}
+
+#define TESTDSPINST_LBUX(index, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS", %1 \n\t" \
+ "move $" #RT", %2 \n\t" \
+ "lbux %0, $" #RT "($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (index) \
+ : #RT, #RS, "memory" \
+ ); \
+ printf("lbux :: out: 0x%08x mem[%d]\n", out, index); \
+}
+
+#define TESTDSPINST_HILO(ac, RSval_hi, RSval_lo) \
+{ \
+ unsigned int HI = 0xdeadbeef; \
+ unsigned int LO = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $t0, %2 \n\t" \
+ "move $t1, %3 \n\t" \
+ "mthi $t0, $" ac " \n\t" \
+ "mtlo $t1, $" ac " \n\t" \
+ "mfhi %0, $" ac " \n\t" \
+ "mflo %1, $" ac " \n\t" \
+ : "=&r" (HI), "=&r" (LO) \
+ : "r" (RSval_hi), "r" (RSval_lo) \
+ : "t0", "t1" \
+ ); \
+ printf("rs_hi: 0x%08x rs_lo: 0x%08x %s out HI: 0x%08x, out LO: 0x%08x\n", \
+ RSval_hi, RSval_lo, ac, HI, LO); \
+}
+
+#define TESTDSPINST_MTHLIP(instruction, ac, HIval, LOval, RSval, RS, pos) \
+{ \
+ unsigned int outHI; \
+ unsigned int outLO; \
+ unsigned int dspCtrl; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %3\n\t" \
+ "mthi $" #RS", $" ac "\n\t" \
+ "move $" #RS ", %4\n\t" \
+ "mtlo $" #RS", $" ac "\n\t" \
+ "move $" #RS ", %5\n\t" \
+ "wrdsp $" #RS ", 0x1 \n\t" \
+ "move $" #RS ", %6\n\t" \
+ instruction "\n\t" \
+ "mfhi %0, $" ac "\n\t" \
+ "mflo %1, $" ac "\n\t" \
+ "rddsp %2, 0x1 \n\t" \
+ : "=&r" (outHI), "=&r" (outLO), "=&r" (dspCtrl) \
+ : "r" (HIval), "r" (LOval), "r" (pos), "r" (RSval) \
+ : #RS \
+ ); \
+ printf("mthlip :: acIn: 0x%08x%08x rsIn 0x%08x posIn 0x%08x acOut 0x%08x%08x\
+ posOut 0x%08x\n", HIval, LOval, RSval, pos, outHI, outLO, dspCtrl); \
+}
+
+#define TESTDSPINST_PICK(instruction, instruction1, RSval, RTval, RD, RS, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl1 = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "wrdsp $zero, 0x1f \n\t" \
+ "move $" #RS ", %2 \n\t" \
+ "move $" #RT ", %3 \n\t" \
+ instruction1 " \n\t" \
+ "rddsp %1, 0x1f \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl1) \
+ : "r" (RSval), "r"(RTval) \
+ : #RD, #RS, #RT \
+ ); \
+ printf("%s :: %s rs 0x%08x rt 0x%08x out 0x%08x DSPCtrl1 0x%x\n", \
+ instruction, instruction1, RSval, RTval, out, dspCtrl1); \
+}
+
+#define TESTDSPINST_RADDU_W_QB(instruction, RSval, RD, RS) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %1 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, #RS \
+ ); \
+ printf("%s :: out 0x%08x rs 0x%08x\n", \
+ instruction, out, RSval); \
+}
+
+#define TESTDSPINST_RDDSPWRDSP(REGval, mask) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $t0, %1 \n\t" \
+ "wrdsp $t0, " #mask " \n\t" \
+ "rddsp %0, " #mask " \n\t" \
+ : "=&r" (out) \
+ : "r" (REGval) \
+ : "t0" \
+ ); \
+ printf("outVal 0x%08x inVal 0x%08x mask 0x%08x \n", out, REGval, mask); \
+}
+
+#define TESTDSPINST_RD_IMM_NODSPC(instruction, Imm, RD) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : \
+ : #RD \
+ ); \
+ printf("%s :: rd 0x%08x imm 0x%08x\n", instruction, out, Imm); \
+}
+
+#define TESTDSPINST_SHILO(ac, HIval, LOval, shift) \
+{ \
+ int outHI = 0xdeadbeef; \
+ int outLO = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $t0, %2 \n\t" \
+ "move $t1, %3 \n\t" \
+ "mthi $t0, $" ac " \n\t" \
+ "mtlo $t1, $" ac " \n\t" \
+ "shilo $" ac ", " #shift " \n\t" \
+ "mfhi %0, $" ac " \n\t" \
+ "mflo %1, $" ac " \n\t" \
+ : "=&r" (outHI), "=&r" (outLO) \
+ : "r" (HIval), "r" (LOval) \
+ : "t0", "t1" \
+ ); \
+ printf("shilo %s, %3d inAcc = 0x%08x%08x outAcc = 0x%08x%08x\n", ac, shift, \
+ HIval, LOval, outHI, outLO); \
+}
+
+#define TESTDSP_SHILOV(ac, HIval, LOval, RSval, RS) \
+{ \
+ int outHI = 0xdeadbeef; \
+ int outLO = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "move $" #RS ", %2 \n\t" \
+ "mthi $" #RS ", $" ac " \n\t" \
+ "move $" #RS ", %3 \n\t" \
+ "mtlo $" #RS ", $" ac " \n\t" \
+ "move $" #RS ", %4 \n\t" \
+ "shilov $" ac ", $" #RS " \n\t" \
+ "mfhi %0, $" ac " \n\t" \
+ "mflo %1, $" ac " \n\t" \
+ : "=&r" (outHI), "=&r" (outLO) \
+ : "r" (HIval), "r" (LOval), "r" (RSval) \
+ : #RS \
+ ); \
+ printf("shilov %s, rs 0x%08x inAcc = 0x%08x%08x outAcc = 0x%08x%08x\n", ac, \
+ RSval, HIval, LOval, outHI, outLO); \
+}
+
+#define TESTDSPINST_RD_RT_SA_DSPC(instruction, RTval, SAval, RD, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "wrdsp $zero, 0x3f \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ instruction " \n\t" \
+ "rddsp %1, 0x3f \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl) \
+ : "r"(RTval) \
+ : #RD, #RT \
+ ); \
+ printf("%s :: rd 0x%08x rt 0x%08x sa %2d DSPCtrl 0x%08x\n", instruction, \
+ out, RTval, SAval, dspCtrl); \
+}
+
+#define TESTDSPINST_RD_RT_SA_NODSPC(instruction, RTval, SAval, RD, RT) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "move $" #RT ", %1 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : "r"(RTval) \
+ : #RD, #RT \
+ ); \
+ printf("%s :: rd 0x%08x rt 0x%08x sa %2d\n", instruction, out, RTval, \
+ SAval); \
+}
+
+#define TESTDSPINST_RD_RT_RS_DSPC(instruction, RTval, RSval, RD, RT, RS) \
+{ \
+ int out = 0xdeadbeef; \
+ int dspCtrl = 0x0; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "wrdsp $zero, 0x3f \n\t" \
+ "move $" #RT ", %2 \n\t" \
+ "move $" #RS ", %3 \n\t" \
+ instruction " \n\t" \
+ "rddsp %1, 0x3f \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out), "=&r" (dspCtrl) \
+ : "r"(RTval), "r"(RSval) \
+ : #RD, #RT, #RS \
+ ); \
+ printf("%s :: rd 0x%08x rt 0x%08x rs 0x%08x DSPCtrl 0x%08x\n", instruction, \
+ out, RTval, RSval, dspCtrl); \
+}
+
+#define TESTDSPINST_RD_RT_RS_NODSPC(instruction, RTval, RSval, RD, RT, RS) \
+{ \
+ int out = 0xdeadbeef; \
+ __asm__ volatile( \
+ ".set dsp; \n\t" \
+ "li $" #RD ", 0 \n\t" \
+ "move $" #RT ", %1 \n\t" \
+ "move $" #RS ", %2 \n\t" \
+ instruction " \n\t" \
+ "move %0, $" #RD " \n\t" \
+ : "=&r" (out) \
+ : "r"(RTval), "r"(RSval) \
+ : #RD, #RT, #RS \
+ ); \
+ printf("%s :: rd 0x%08x rt 0x%08x rs 0x%08x\n", instruction, out, RTval, \
+ RSval); \
+}
+
+int main(int argc, char **argv)
+{
+ printf("-------- ABSQ_S.PH --------\n");
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x00000000, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0x00000286, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xfabc2435, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x73468000, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x80000000, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0xffffffff, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xfff45fff, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0x00000555, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x23534870, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0x0555adec, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0x980b7cde, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0xf973437b, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x93474bde, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0x55555555, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xc4dbfe20, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0x734680bc, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x00354565, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0xbacabaca, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xdecadeca, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x00000286, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0xabababab, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0x00086755, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0x8f8f8f80, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0xeeeeeeee, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x1bdbdbdb, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0xdecadeca, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0x93474bde, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0xfabfabfa, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x083b3571, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0xb9743941, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xbc80f924, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0xcc3c201c, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x1ebaf88e, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0x722d5e20, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xa1d6f791, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x7b11bee7, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0xa5631488, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0xb10bcc65, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0x73f39fca, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0x80008000, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", -23456, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 123498746, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", -13, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", -237, t6, t7);
+
+ printf("-------- ABSQ_S.W --------\n");
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x00000000, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0x00000286, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xfabc2435, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x73468000, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x80000000, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0xffffffff, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xfff45fff, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0x00000555, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x23534870, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0x0555adec, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0x980b7cde, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0xf973437b, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x93474bde, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0x55555555, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xc4dbfe20, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0x734680bc, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x00354565, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0xbacabaca, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xdecadeca, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x00000286, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0xabababab, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0x00086755, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0x8f8f8f80, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0xeeeeeeee, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x1bdbdbdb, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0xdecadeca, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0x93474bde, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0xfabfabfa, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x083b3571, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0xb9743941, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xbc80f924, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0xcc3c201c, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x1ebaf88e, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0x722d5e20, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xa1d6f791, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x7b11bee7, t6, t7);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0xa5631488, t5, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0xb10bcc65, t2, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0x73f39fca, t0, t8);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0x80000000, t4, t4);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", -23456, t0, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 123498746, t2, t3);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", -13, t4, t1);
+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", -237, t6, t7);
+
+ printf("-------- ADDQ.PH --------\n");
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x00045fb2, 0x00000286,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t1, $t5", 0x00002435, 0xffff3421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0xf973437b, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x00000004, 1073741824,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t1, $t5", 0x80002435, 0x80003421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0x76548000, 0x73468000,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0x80000000, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x80000000, 0x80000000,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0x00000018, 0xffff2435,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0xbabababa, 0xabababab,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0xfbde3976, 0x00000000,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x23534870, 0x00354565,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x980b7cde, 0x00086755,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0xffffffff, 0xffffffff,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313,
+ t4, t6, t1);
+
+ printf("-------- ADDQ_S.PH --------\n");
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00045fb2, 0x00000286,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x00002435, 0xffff3421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xf973437b, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00000004, 1073741824,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x80002435, 0x80003421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x76548000, 0x73468000,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x80000000, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x80000000, 0x80000000,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x00000018, 0xffff2435,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xbabababa, 0xabababab,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xfbde3976, 0x00000000,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x23534870, 0x00354565,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x980b7cde, 0x00086755,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xffffffff, 0xffffffff,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313,
+ t4, t6, t1);
+
+ printf("-------- ADDQ_S.W --------\n");
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00045fb2, 0x00000286,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x00002435, 0xffff3421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xf973437b, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00000004, 1073741824,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x80002435, 0x80003421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x76548000, 0x73468000,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x80000000, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x80000000, 0x80000000,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x00000018, 0xffff2435,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xbabababa, 0xabababab,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0xfbde3976, 0x00000000,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x23534870, 0x00354565,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x980b7cde, 0x00086755,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x92784656, 0xeeeeeeee,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xbacabaca, 0xdecadeca,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x12fadeb4, 0x93474bde,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7c000790, 0xfc0007ff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0xffffffff, 0xffffffff,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x2106ba5f, 0x87df4510,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x638ca515, 0x006a54f2,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313,
+ t4, t6, t1);
+
+ printf("-------- ADDSC --------\n");
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00045fb2, 0x00000286,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x00002435, 0xffff3421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x07654cb8, 0x734680bc,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xf973437b, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00000004, 1073741824,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x80002435, 0x80003421,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x76548000, 0x73468000,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x80000000, 0x80000000,
+ t5, t3, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xffffffff,
+ t2, t4, t8);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff,
+ t0, t8, t0);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0000c420, 0x00000555,
+ t4, t6, t1);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x00000000, 0x00000000,
+ t0, t1, t2);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x80000000, 0x80000000,
+ t2, t3, t4);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555,
+ t4, t1, t5);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x00000018, 0xffff2435,
+ t6, t7, t3);
+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, ...
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