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From: <sv...@va...> - 2013-05-28 16:51:44
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petarj 2013-05-28 17:51:27 +0100 (Tue, 28 May 2013)
New Revision: 13410
Log:
mips64: set of mips64 specific tests
This is a set of mips64 programs that test mips64 instruction set.
Added files:
trunk/none/tests/mips64/arithmetic_instruction.c
trunk/none/tests/mips64/branch_and_jump_instructions.c
trunk/none/tests/mips64/branches.c
trunk/none/tests/mips64/const.h
trunk/none/tests/mips64/extract_insert_bit_field.c
trunk/none/tests/mips64/fpu_arithmetic.c
trunk/none/tests/mips64/fpu_branches.c
trunk/none/tests/mips64/fpu_control_word.c
trunk/none/tests/mips64/fpu_load_store.c
trunk/none/tests/mips64/load_store.c
trunk/none/tests/mips64/load_store_multiple.c
trunk/none/tests/mips64/load_store_unaligned.c
trunk/none/tests/mips64/logical_instructions.c
trunk/none/tests/mips64/macro_fpu.h
trunk/none/tests/mips64/macro_int.h
trunk/none/tests/mips64/macro_load_store.h
trunk/none/tests/mips64/move_instructions.c
trunk/none/tests/mips64/rotate_swap.c
trunk/none/tests/mips64/round.c
trunk/none/tests/mips64/rounding_mode.h
trunk/none/tests/mips64/shift_instructions.c
trunk/none/tests/mips64/test_block_size.c
trunk/none/tests/mips64/unaligned_load.c
Modified files:
trunk/none/tests/mips64/Makefile.am
Added: trunk/none/tests/mips64/rounding_mode.h (+61 -0)
===================================================================
--- trunk/none/tests/mips64/rounding_mode.h 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/rounding_mode.h 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,61 @@
+typedef enum {
+ TO_NEAREST=0,
+ TO_ZERO,
+ TO_PLUS_INFINITY,
+ TO_MINUS_INFINITY
+} round_mode_t;
+
+char *round_mode_name[] = { "near", "zero", "+inf", "-inf" };
+
+void set_rounding_mode(round_mode_t mode)
+{
+ switch(mode) {
+ case TO_NEAREST:
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "srl $t0, 2" "\n\t"
+ "sll $t0, 2" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+ break;
+ case TO_ZERO:
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "srl $t0, 2" "\n\t"
+ "sll $t0, 2" "\n\t"
+ "addiu $t0, 1" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+ break;
+ case TO_PLUS_INFINITY:
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "srl $t0, 2" "\n\t"
+ "sll $t0, 2" "\n\t"
+ "addiu $t0, 2" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+ break;
+ case TO_MINUS_INFINITY:
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "srl $t0, 2" "\n\t"
+ "sll $t0, 2" "\n\t"
+ "addiu $t0, 3" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+ break;
+ }
+}
Added: trunk/none/tests/mips64/macro_fpu.h (+338 -0)
===================================================================
--- trunk/none/tests/mips64/macro_fpu.h 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/macro_fpu.h 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,338 @@
+#include "const.h"
+
+typedef enum {
+ ABSS=0, ABSD, ADDS, ADDD,
+ DIVS, DIVD, MULS, MULD,
+ NEGS, NEGD, SQRTS, SQRTD,
+ SUBS, SUBD, RECIPS, RECIPD,
+ RSQRTS, RSQRTD, MSUBS, MSUBD,
+ MADDS, MADDD, NMADDS, NMADDD,
+ NMSUBS, NMSUBD
+} flt_art_op_t;
+
+typedef enum {
+ CEILWS=0, CEILWD, FLOORWS, FLOORWD,
+ ROUNDWS, ROUNDWD, TRUNCWS, TRUNCWD,
+ CEILLS, CEILLD, FLOORLS, FLOORLD,
+ ROUNDLS, ROUNDLD, TRUNCLS, TRUNCLD
+} flt_dir_op_t;
+
+typedef enum {
+ CVTDS, CVTDW, CVTSD, CVTSW,
+ CVTWS, CVTWD, CVTDL, CVTLS,
+ CVTLD, CVTSL,
+} flt_round_op_t;
+
+const char *flt_art_op_names[] = {
+ "abs.s", "abs.d", "add.s", "add.d",
+ "div.s", "div.d", "mul.s", "mul.d",
+ "neg.s", "neg.d", "sqrt.s", "sqrt.d",
+ "sub.s", "sub.d", "recip.s", "recip.d",
+ "rsqrt.s", "rsqrt.d", "msub.s", "msub.d",
+ "madd.s", "madd.d", "nmadd.s", "nmadd.d",
+ "nmsub.s", "nmsub.d"
+};
+
+const char *flt_dir_op_names[] = {
+ "ceil.w.s", "ceil.w.d",
+ "floor.w.s", "floor.w.d",
+ "round.w.s", "round.w.d",
+ "trunc.w.s", "trunc.w.d",
+ "ceil.l.s", "ceil.l.d",
+ "floor.l.s", "floor.l.d",
+ "round.l.s", "round.l.d",
+ "trunc.l.s", "trunc.l.d"
+};
+
+const char *flt_round_op_names[] = {
+ "cvt.d.s", "cvt.d.w",
+ "cvt.s.d", "cvt.s.w",
+ "cvt.w.s", "cvt.w.d",
+ "cvt.d.l", "cvt.l.s",
+ "cvt.l.d", "cvt.s.l",
+};
+
+#define UNOPdd(op) \
+ fd_d = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1" "\n\t" \
+ : "=f"(fd_d) \
+ : "f"(fs_d[i]) \
+ );
+
+#define UNOPff(op) \
+ fd_f = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1" "\n\t" \
+ : "=f"(fd_f) \
+ : "f"(fs_f[i]) \
+ );
+
+#define UNOPfd(op) \
+ fd_d = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1" "\n\t" \
+ : "=f"(fd_d) \
+ : "f"(fs_f[i]) \
+ );
+
+#define UNOPdf(op) \
+ fd_f = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1" "\n\t" \
+ : "=f"(fd_f) \
+ : "f"(fs_d[i]) \
+ );
+
+#define UNOPfw(op) \
+ fd_w = 0; \
+ __asm__ __volatile__( \
+ op" $f0, %1" "\n\t" \
+ "mfc1 %0, $f0" "\n\t" \
+ : "=r"(fd_w) \
+ : "f"(fs_f[i]) \
+ : "$f0" \
+ );
+
+#define UNOPdw(op) \
+ fd_w = 0; \
+ __asm__ __volatile__( \
+ op" $f0, %1" "\n\t" \
+ "mfc1 %0, $f0" "\n\t" \
+ : "=r"(fd_w) \
+ : "f"(fs_d[i]) \
+ : "$f0" \
+ );
+
+#define UNOPwd(op) \
+ fd_d = 0; \
+ __asm__ __volatile__( \
+ "mtc1 %1, $f0" "\n\t" \
+ op" %0, $f0" "\n\t" \
+ : "=f"(fd_d) \
+ : "r"(fs_w[i]) \
+ : "$f0" \
+ );
+
+#define UNOPwf(op) \
+ fd_f = 0; \
+ __asm__ __volatile__( \
+ "mtc1 %1, $f0" "\n\t" \
+ op" %0, $f0" "\n\t" \
+ : "=f"(fd_f) \
+ : "r"(fs_w[i]) \
+ : "$f0" \
+ );
+
+#define UNOPld(op) \
+ fd_d = 0; \
+ __asm__ __volatile__( \
+ "dmtc1 %1, $f0" "\n\t" \
+ op" %0, $f0" "\n\t" \
+ : "=f"(fd_d) \
+ : "r"(fs_l[i]) \
+ : "$f0" \
+ );
+
+#define UNOPdl(op) \
+ fd_l = 0; \
+ __asm__ __volatile__( \
+ op" $f0, %1" "\n\t" \
+ "dmfc1 %0, $f0" "\n\t" \
+ : "=r"(fd_l) \
+ : "f"(fs_d[i]) \
+ : "$f0" \
+ );
+
+#define UNOPls(op) \
+ fd_f = 0; \
+ __asm__ __volatile__( \
+ "dmtc1 %1, $f0" "\n\t" \
+ op" %0, $f0" "\n\t" \
+ : "=f"(fd_f) \
+ : "r"(fs_l[i]) \
+ : "$f0" \
+ );
+
+#define UNOPsl(op) \
+ fd_l = 0; \
+ __asm__ __volatile__( \
+ op" $f0, %1" "\n\t" \
+ "dmfc1 %0, $f0" "\n\t" \
+ : "=r"(fd_l) \
+ : "f"(fs_f[i]) \
+ : "$f0" \
+ );
+
+#define BINOPf(op) \
+ fd_f = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1, %2" "\n\t" \
+ : "=f" (fd_f) \
+ : "f" (fs_f[i]), "f" (ft_f[i]) \
+ );
+
+#define BINOPd(op) \
+ fd_d = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1, %2" "\n\t" \
+ : "=f"(fd_d) \
+ : "f" (fs_d[i]), "f" (ft_d[i]) \
+ );
+
+#define TRIOPf(op) \
+ fd_f = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1, %2, %3" "\n\t" \
+ : "=f" (fd_f) \
+ : "f" (fr_f[i]), "f" (fs_f[i]) , "f" (ft_f[i]) \
+ );
+
+#define TRIOPd(op) \
+ fd_d = 0; \
+ __asm__ __volatile__( \
+ op" %0, %1, %2, %3" "\n\t" \
+ : "=f"(fd_d) \
+ : "f" (fr_d[i]), "f" (fs_d[i]) , "f" (ft_d[i]) \
+ );
+
+/* Conditional macros.*/
+#define TESTINST1s(instruction, RDval) \
+{ \
+ float outf = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "mov.s $f1, %1" "\n\t" \
+ "mov.s $f2, %2" "\n\t" \
+ "mtc1 $zero, $f0" "\n\t" \
+ "c.eq.s $f1, $f2" "\n\t" \
+ instruction" end"instruction"s"#RDval "\n\t" \
+ "nop" "\n\t" \
+ "add.s $f0, $f0, $f1" "\n\t" \
+ "end"instruction"s"#RDval":" "\n\t" \
+ "add.s $f0, $f0, $f2" "\n\t" \
+ "mov.s %0, $f0" "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=f" (outf) \
+ : "f" (fs_f[i]) , "f" (ft_f[i]) \
+ : "$f0", "$f1", "$f2" \
+ ); \
+ printf("%s, c.eq.s out=%f, fs=%f, ft=%f\n", \
+ instruction, outf, fs_f[i], ft_f[i]); \
+}
+
+#define TESTINST1d(instruction, RDval) \
+{ \
+ double outd = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "mov.d $f1, %1" "\n\t" \
+ "mov.d $f2, %2" "\n\t" \
+ "dmtc1 $zero, $f0" "\n\t" \
+ "c.eq.d $f1, $f2" "\n\t" \
+ instruction" end"instruction"d"#RDval "\n\t" \
+ "nop" "\n\t" \
+ "add.d $f0, $f0, $f1" "\n\t" \
+ "end"instruction"d"#RDval":" "\n\t" \
+ "add.d $f0, $f0, $f2" "\n\t" \
+ "mov.d %0, $f0" "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=f" (outd) \
+ : "f" (fs_d[i]) , "f" (ft_d[i]) \
+ : "$f0", "$f1", "$f2" \
+ ); \
+ printf("%s, c.eq.d out=%f, fs=%f, ft=%f\n", \
+ instruction, outd, fs_d[i], ft_d[i]); \
+}
+
+#define TESTINST2s(instruction, RDval) \
+{ \
+ float outf = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "mov.s $f1, %1" "\n\t" \
+ "mov.s $f2, %2" "\n\t" \
+ "mtc1 $zero, $f0" "\n\t" \
+ "c.eq.s $f1, $f2" "\n\t" \
+ instruction" end"instruction"s"#RDval "\n\t" \
+ "add.s $f0, $f0, $f1" "\n\t" \
+ "end"instruction"s"#RDval":" "\n\t" \
+ "add.s $f0, $f0, $f2" "\n\t" \
+ "mov.s %0, $f0" "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=f" (outf) \
+ : "f" (fs_f[i]) , "f" (ft_f[i]) \
+ : "$f0", "$f1", "$f2" \
+ ); \
+ printf("%s, c.eq.s out=%f, fs=%f, ft=%f\n", \
+ instruction, outf, fs_f[i], ft_f[i]); \
+}
+
+#define TESTINST2d(instruction, RDval) \
+{ \
+ double outd = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "mov.d $f1, %1" "\n\t" \
+ "mov.d $f2, %2" "\n\t" \
+ "dmtc1 $zero, $f0" "\n\t" \
+ "c.eq.d $f1, $f2" "\n\t" \
+ instruction" end"instruction"d"#RDval "\n\t" \
+ "add.d $f0, $f0, $f1" "\n\t" \
+ "end"instruction"d"#RDval":" "\n\t" \
+ "add.d $f0, $f0, $f2" "\n\t" \
+ "mov.d %0, $f0" "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=f" (outd) \
+ : "f" (fs_d[i]) , "f" (ft_d[i]) \
+ : "$f0", "$f1", "$f2" \
+ ); \
+ printf("%s, c.eq.d out=%f, fs=%f, ft=%f\n", \
+ instruction, outd, fs_d[i], ft_d[i]); \
+}
+
+#define TESTINST_CONDs(instruction, RDval) \
+{ \
+ float outf = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "mov.s $f1, %1" "\n\t" \
+ "mov.s $f2, %2" "\n\t" \
+ "mov.s $f0, %1" "\n\t" \
+ instruction" $f1, $f2" "\n\t" \
+ "bc1f end"instruction"s"#RDval "\n\t" \
+ "nop" "\n\t" \
+ "add.s $f0, $f0, $f2" "\n\t" \
+ "end"instruction"s"#RDval":" "\n\t" \
+ "mov.s %0, $f0" "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=f" (outf) \
+ : "f" (fs_f[i]) , "f" (ft_f[i]) \
+ : "$f0", "$f1", "$f2" \
+ ); \
+ printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \
+ instruction, outf, fs_f[i], ft_f[i]); \
+}
+
+#define TESTINST_CONDd(instruction, RDval) \
+{ \
+ double outd = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "mov.d $f1, %1" "\n\t" \
+ "mov.d $f2, %2" "\n\t" \
+ "mov.d $f0, %1" "\n\t" \
+ instruction" $f1, $f2" "\n\t" \
+ "bc1f end"instruction"d"#RDval "\n\t" \
+ "nop" "\n\t" \
+ "add.d $f0, $f0, $f2" "\n\t" \
+ "end"instruction"d"#RDval":" "\n\t" \
+ "mov.d %0, $f0" "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=f" (outd) \
+ : "f" (fs_d[i]) , "f" (ft_d[i]) \
+ : "$f0", "$f1", "$f2" \
+ ); \
+ printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \
+ instruction, outd, fs_d[i], ft_d[i]); \
+}
Modified: trunk/none/tests/mips64/Makefile.am (+55 -2)
===================================================================
--- trunk/none/tests/mips64/Makefile.am 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/Makefile.am 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -3,12 +3,65 @@
dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ arithmetic_instruction.stdout.exp-mips64 \
+ arithmetic_instruction.stdout.exp-mips64r2 arithmetic_instruction.stderr.exp \
+ arithmetic_instruction.vgtest \
+ branch_and_jump_instructions.stdout.exp \
+ branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \
+ branches.stdout.exp branches.stderr.exp branches.vgtest
+ extract_insert_bit_field.stdout.exp-mips64 \
+ extract_insert_bit_field.stdout.exp-mips64r2 \
+ extract_insert_bit_field.stderr.exp extract_insert_bit_field.vgtest \
+ fpu_arithmetic.stdout.exp fpu_arithmetic.stderr.exp fpu_arithmetic.vgtest \
+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
+ fpu_control_word.stdout.exp fpu_control_word.stderr.exp \
+ fpu_control_word.vgtest \
+ fpu_load_store.stdout.exp-BE fpu_load_store.stdout.exp-LE \
+ fpu_load_store.stderr.exp fpu_load_store.vgtest \
+ load_store.stdout.exp-BE load_store.stdout.exp-LE load_store.stderr.exp \
+ load_store.vgtest \
+ load_store_multiple.stdout.exp-BE load_store_multiple.stdout.exp-LE \
+ load_store_multiple.stderr.exp load_store_multiple.vgtest \
+ load_store_unaligned.stdout.exp load_store_unaligned.stderr.exp \
+ load_store_unaligned.vgtest \
+ logical_instructions.stdout.exp logical_instructions.stderr.exp \
+ logical_instructions.vgtest \
+ move_instructions.stdout.exp-BE move_instructions.stdout.exp-LE \
+ move_instructions.stderr.exp move_instructions.vgtest \
+ rotate_swap.stdout.exp-mips64 rotate_swap.stdout.exp-mips64r2 \
+ rotate_swap.stderr.exp rotate_swap.vgtest \
+ round.stdout.exp round.stderr.exp round.vgtest \
+ shift_instructions.stdout-exp-mips64 shift_instructions.stdout-exp-mips64r2 \
+ shift_instructions.stderr.exp shift_instructions.vgtest \
+ test_block_size.stdout.exp test_block_size.stderr.exp \
+ test_block_size.vgtest \
+ unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
+ unaligned_load.stderr.exp unaligned_load.vgtest
+
check_PROGRAMS = \
- allexec
+ allexec \
+ arithmetic_instruction \
+ branch_and_jump_instructions \
+ branches \
+ extract_insert_bit_field \
+ fpu_arithmetic \
+ fpu_branches \
+ fpu_control_word \
+ fpu_load_store \
+ load_store \
+ load_store_multiple \
+ load_store_unaligned \
+ logical_instructions \
+ move_instructions \
+ rotate_swap \
+ round \
+ shift_instructions \
+ test_block_size \
+ unaligned_load
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
-
Added: trunk/none/tests/mips64/logical_instructions.c (+103 -0)
===================================================================
--- trunk/none/tests/mips64/logical_instructions.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/logical_instructions.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,103 @@
+#include <stdio.h>
+#include "const.h"
+#include "macro_int.h"
+
+typedef enum {
+ AND=0, ANDI, LUI, NOR,
+ OR, ORI, XOR, XORI
+} logical_op;
+
+int main()
+{
+ logical_op op;
+ int i;
+ init_reg_val2();
+ for (op = AND; op <= XORI; op++) {
+ for (i = 0; i < N; i++) {
+ switch (op) {
+ case AND:
+ /* No Integer Overflow exception occurs under any
+ circumstances. */
+ TEST1("and $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("and $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case ANDI:
+ /* No Integer Overflow exception occurs under any
+ circumstances. */
+ TEST2("andi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
+ TEST2("andi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
+ TEST2("andi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
+ TEST2("andi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
+ TEST2("andi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
+ TEST2("andi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
+ TEST2("andi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
+ TEST2("andi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
+ break;
+
+ case LUI:
+ /* No Integer Overflow exception occurs under any
+ circumstances. */
+ if (i == 0) {
+ TEST6("lui $t0, 0xffff", 0xffff, t0);
+ TEST6("lui $a0, 0x0", 0x0, a0);
+ TEST6("lui $t9, 0xff", 0xff, t9);
+ TEST6("lui $v0, 0xfff", 0xfff, v0);
+ TEST6("lui $s0, 0x2", 0x2, s0);
+ }
+ break;
+
+ case NOR:
+ /* No arithmetic exception occurs under any circumstances. */
+ TEST1("nor $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("nor $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case OR:
+ /* No arithmetic exception occurs under any circumstances. */
+ TEST1("or $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("or $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case ORI:
+ /* No arithmetic exception occurs under any circumstances. */
+ TEST2("ori $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
+ TEST2("ori $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
+ TEST2("ori $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
+ TEST2("ori $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
+ TEST2("ori $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
+ TEST2("ori $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
+ TEST2("ori $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
+ TEST2("ori $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
+ break;
+
+ case XOR:
+ /* No arithmetic exception occurs under any circumstances. */
+ TEST1("xor $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("xor $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case XORI:
+ /* No arithmetic exception occurs under any circumstances. */
+ TEST2("xori $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
+ TEST2("xori $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
+ TEST2("xori $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
+ TEST2("xori $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
+ TEST2("xori $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
+ TEST2("xori $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
+ TEST2("xori $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
+ TEST2("xori $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
+ break;
+ }
+ }
+ }
+ return 0;
+}
Added: trunk/none/tests/mips64/shift_instructions.c (+205 -0)
===================================================================
--- trunk/none/tests/mips64/shift_instructions.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/shift_instructions.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,205 @@
+#include <stdio.h>
+#include "const.h"
+#include "macro_int.h"
+
+typedef enum {
+ DROTR=0, DROTR32, DROTRV, DSLL,
+ DSLL32, DSLLV, DSRA, DSRA32,
+ DSRAV, DSRL, DSRL32, DSRLV,
+ ROTR, ROTRV, SLL, SLLV,
+ SRA, SRAV, SRL, SRLV
+} logical_op;
+
+int main()
+{
+ logical_op op;
+ int i;
+ init_reg_val2();
+ for (op = DROTR; op <= SRLV; op++) {
+ for (i = 0; i < N; i++) {
+ switch(op) {
+ case DROTR:
+ /* Release 2 Only */
+#if (__mips == 64) && (__mips_isa_rev >= 2)
+ TEST2("drotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("drotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("drotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("drotr $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("drotr $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("drotr $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("drotr $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+#endif
+ break;
+ case DROTR32:
+ /* Release 2 Only */
+#if (__mips == 64) && (__mips_isa_rev >= 2)
+ TEST2("drotr32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("drotr32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("drotr32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("drotr32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("drotr32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("drotr32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("drotr32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("drotr32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+#endif
+ break;
+ case DROTRV:
+ /* Release 2 Only */
+#if (__mips == 64) && (__mips_isa_rev >= 2)
+ TEST1("drotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("drotrv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+#endif
+ break;
+ case DSLL:
+ TEST2("dsll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("dsll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("dsll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("dsll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("dsll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("dsll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("dsll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("dsll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case DSLL32:
+ TEST2("dsll32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("dsll32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("dsll32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("dsll32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("dsll32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("dsll32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("dsll32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("dsll32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case DSLLV:
+ TEST1("dsllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("dsllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case DSRA:
+ TEST2("dsra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("dsra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("dsra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("dsra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("dsra $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("dsra $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("dsra $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("dsra $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case DSRA32:
+ TEST2("dsra32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("dsra32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("dsra32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("dsra32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("dsra32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("dsra32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("dsra32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("dsra32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case DSRAV:
+ TEST1("dsrav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("dsrav $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case DSRL:
+ TEST2("dsrl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("dsrl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("dsrl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("dsrl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("dsrl $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("dsrl $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("dsrl $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("dsrl $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case DSRL32:
+ TEST2("dsrl32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("dsrl32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("dsrl32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("dsrl32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("dsrl32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("dsrl32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("dsrl32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("dsrl32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case DSRLV:
+ TEST1("dsrlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("dsrlv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case ROTR:
+ /* Release 2 Only */
+#if (__mips == 64) && (__mips_isa_rev >= 2)
+ TEST2("rotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("rotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("rotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+#endif
+ break;
+ case ROTRV:
+ /* Release 2 Only */
+#if (__mips == 64) && (__mips_isa_rev >= 2)
+ TEST1("rotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+#endif
+ break;
+ case SLL:
+ TEST2("sll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("sll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("sll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("sll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ TEST2("sll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
+ TEST2("sll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
+ TEST2("sll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
+ TEST2("sll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
+ break;
+
+ case SLLV:
+ TEST1("sllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ TEST1("sllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
+ s0, s1, s2);
+ break;
+
+ case SRA:
+ TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ break;
+
+ case SRAV:
+ TEST1("srav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ break;
+
+ case SRL:
+ TEST2("srl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
+ TEST2("srl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
+ TEST2("srl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
+ TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
+ break;
+
+ case SRLV:
+ TEST1("srlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
+ t0, t1, t2);
+ break;
+
+ }
+ }
+ }
+ return 0;
+}
Added: trunk/none/tests/mips64/rotate_swap.c (+192 -0)
===================================================================
--- trunk/none/tests/mips64/rotate_swap.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/rotate_swap.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,192 @@
+#include <stdio.h>
+
+#define TESTINST_DROTR(instruction, in, SA) \
+{ \
+ unsigned long long out; \
+ __asm__ __volatile__( \
+ "move $t0, $zero" "\n\t" \
+ "move $t1, %1" "\n\t" \
+ instruction" $t0, $t1, "#SA "\n\t" \
+ "move %0, $t0" "\n\t" \
+ : "=r" (out) \
+ : "r" (in) \
+ : "t0", "t1" \
+ ); \
+ printf("%s :: in 0x%llx, out 0x%llx, SA %d\n", \
+ instruction, (long long) in, out, SA); \
+}
+
+#define TESTINST_DROTRV(instruction, in, SA) \
+{ \
+ unsigned long long out; \
+ __asm__ __volatile__( \
+ "move $t0, $zero" "\n\t" \
+ "move $t1, %1" "\n\t" \
+ "move $t2, %2" "\n\t" \
+ instruction" $t0, $t1, $t2" "\n\t" \
+ "move %0, $t0" "\n\t" \
+ : "=r" (out) \
+ : "r" (in), "r" (SA) \
+ : "t0", "t1", "t2" \
+ ); \
+ printf("%s :: in 0x%llx, out 0x%llx, SA %d\n", \
+ instruction, (long long) in, out, SA); \
+}
+
+#define TESTINST_DSWAP(instruction, in) \
+{ \
+ unsigned long long out; \
+ __asm__ __volatile__( \
+ "move $t0, $0" "\n\t" \
+ "move $t1, $0" "\n\t" \
+ "move $t1, %1" "\n\t" \
+ instruction" $t0, $t1" "\n\t" \
+ "move %0, $t0" "\n\t" \
+ : "=r" (out) \
+ : "r" (in) \
+ : "t0", "t1" \
+ ); \
+ printf("%s :: in 0x%llx, out 0x%llx\n", \
+ instruction, (long long) in, out); \
+}
+
+int main()
+{
+#if (__mips == 64) && (__mips_isa_rev >= 2)
+ printf("--- DROTR ---\n");
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 16);
+ TESTINST_DROTR("drotr", 0xffff0000ffffffff, 16);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 8);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 4);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 5);
+ TESTINST_DROTR("drotr", 0x31415927ffffffff, 10);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 4);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 0);
+ TESTINST_DROTR("drotr", 0xeeeeffffffffffff, 16);
+ TESTINST_DROTR("drotr", 0x2000ffffffffbbbb, 31);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 16);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 0);
+ TESTINST_DROTR("drotr", 0x7fffffffffffffff, 16);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 2);
+ TESTINST_DROTR("drotr", 0x2000ffffffffffff, 24);
+ TESTINST_DROTR("drotr", 0xfffffff31415927f, 16);
+ TESTINST_DROTR("drotr", 0xffffffffffff0008, 3);
+ TESTINST_DROTR("drotr", 0xffff0000ffffffff, 16);
+ TESTINST_DROTR("drotr", 0xff0000ffffffffff, 16);
+ TESTINST_DROTR("drotr", 0xfffffffff0000fff, 16);
+
+ printf("--- DROTR32 ---\n");
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 16);
+ TESTINST_DROTR("drotr32", 0xffff0000ffffffff, 16);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 8);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 4);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 5);
+ TESTINST_DROTR("drotr32", 0x31415927ffffffff, 10);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 4);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 0);
+ TESTINST_DROTR("drotr32", 0xeeeeffffffffffff, 16);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 31);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffbbbb, 16);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 0);
+ TESTINST_DROTR("drotr32", 0x7fffffffffffffff, 16);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 2);
+ TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 24);
+ TESTINST_DROTR("drotr32", 0xfffffff31415927f, 16);
+ TESTINST_DROTR("drotr32", 0xffffffffffff0008, 3);
+ TESTINST_DROTR("drotr32", 0xffff0000ffffffff, 16);
+ TESTINST_DROTR("drotr32", 0xff0000ffffffffff, 16);
+ TESTINST_DROTR("drotr32", 0xfffffffff0000fff, 16);
+
+ printf("--- DROTRV ---\n");
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 16);
+ TESTINST_DROTRV("drotrv", 0xffff0000ffffffff, 16);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 8);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 4);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 5);
+ TESTINST_DROTRV("drotrv", 0x31415927ffffffff, 10);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 4);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 0);
+ TESTINST_DROTRV("drotrv", 0xeeeeffffffffffff, 16);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 31);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffbbbb, 16);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 0);
+ TESTINST_DROTRV("drotrv", 0x7fffffffffffffff, 16);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 2);
+ TESTINST_DROTRV("drotrv", 0x2000ffffffffffff, 24);
+ TESTINST_DROTRV("drotrv", 0xfffffff31415927f, 16);
+ TESTINST_DROTRV("drotrv", 0xffffffffffff0008, 3);
+ TESTINST_DROTRV("drotrv", 0xffff0000ffffffff, 16);
+ TESTINST_DROTRV("drotrv", 0xff0000ffffffffff, 16);
+ TESTINST_DROTRV("drotrv", 0xfffffffff0000fff, 16);
+
+ printf("--- DSBH ---\n");
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dsbh", 0xffff0000ffffffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffeeeeffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dsbh", 0x31415927ffffffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffccccff);
+ TESTINST_DSWAP("dsbh", 0xeeeeffffffffffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffff0000ffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffbbbb);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dsbh", 0x7fffffff5555ffff);
+ TESTINST_DSWAP("dsbh", 0x2000ffffff123123);
+ TESTINST_DSWAP("dsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dsbh", 0xfffffff31415927f);
+ TESTINST_DSWAP("dsbh", 0xffffffffffff0008);
+ TESTINST_DSWAP("dsbh", 0xffff0000ffff88ff);
+ TESTINST_DSWAP("dsbh", 0xff0000ffffffffff);
+ TESTINST_DSWAP("dsbh", 0xfff10ffff0000fff);
+
+ printf("--- DSHD ---\n");
+ TESTINST_DSWAP("dshd", 0x2002ffffffffffff);
+ TESTINST_DSWAP("dshd", 0xffff0000ffffffff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffddddff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffeeee);
+ TESTINST_DSWAP("dshd", 0x31415927ffffffff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffaaaa);
+ TESTINST_DSWAP("dshd", 0x2000ffffffbbbbff);
+ TESTINST_DSWAP("dshd", 0xeeeeff33ff22ffff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffbbbb);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dshd", 0x7fffffffddddffff);
+ TESTINST_DSWAP("dshd", 0x2000ffffffff2222);
+ TESTINST_DSWAP("dshd", 0x2000ffffffffffff);
+ TESTINST_DSWAP("dshd", 0xfffffff31415927f);
+ TESTINST_DSWAP("dshd", 0xffffffffffff0008);
+ TESTINST_DSWAP("dshd", 0xffff0000ffffffff);
+ TESTINST_DSWAP("dshd", 0xff0000ffffffffff);
+ TESTINST_DSWAP("dshd", 0xfffffffff0000fff);
+
+ printf("--- WSBH ---\n");
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("wsbh", 0xffff0000ffffffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffeeeeffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("wsbh", 0x31415927ffffffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffccccff);
+ TESTINST_DSWAP("wsbh", 0xeeeeffffffffffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffff0000ffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffbbbb);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("wsbh", 0x7fffffff5555ffff);
+ TESTINST_DSWAP("wsbh", 0x2000ffffff123123);
+ TESTINST_DSWAP("wsbh", 0x2000ffffffffffff);
+ TESTINST_DSWAP("wsbh", 0xfffffff31415927f);
+ TESTINST_DSWAP("wsbh", 0xffffffffffff0008);
+ TESTINST_DSWAP("wsbh", 0xffff0000ffff88ff);
+ TESTINST_DSWAP("wsbh", 0xff0000ffffffffff);
+ TESTINST_DSWAP("wsbh", 0xfff10ffff0000fff);
+#else
+ printf("This test is testing mips64r2 instructions.\n");
+#endif
+
+ return 0;
+}
Added: trunk/none/tests/mips64/load_store.c (+134 -0)
===================================================================
--- trunk/none/tests/mips64/load_store.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/load_store.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,134 @@
+#include <stdio.h>
+#include "macro_load_store.h"
+
+int main()
+{
+ int i;
+ int s1 = sizeof(int);
+ int s2 = sizeof(unsigned long long);
+ init_reg_val2();
+ /**********************************************************************/
+ /*-------------------------------LOAD---------------------------------*/
+ /**********************************************************************/
+ /* lb */
+ for (i = 0; i < N*s1; i++)
+ TEST1("lb", i, reg_val1);
+
+ for (i = 0; i < N*s2; i++)
+ TEST1("lb", i, reg_val2);
+
+ /* lbu */
+ for (i = 0; i < N*s1; i++)
+ TEST1("lbu", i, reg_val1);
+
+ for (i = 0; i < N*s2; i++)
+ TEST1("lbu", i, reg_val2);
+
+ /* ld */
+ for (i = 0; i < N*s1; i = i+8)
+ TEST1("ld", i, reg_val1);
+
+ for (i = 0; i < N*s2; i = i+8)
+ TEST1("ld", i, reg_val2);
+
+ /* ldl */
+ for (i = 0; i < N*s1; i++)
+ TEST1("ldl", i, reg_val1);
+
+ for (i = 0; i < N*s2; i++)
+ TEST1("ldl", i, reg_val2);
+
+ /* ldr */
+ for (i = 0; i < N*s1; i++)
+ TEST1("ldr", i, reg_val1);
+
+ for (i = 0; i < N*s2; i++)
+ TEST1("ldr", i, reg_val2);
+
+ /* lh */
+ for (i = 0; i < N*s1; i = i+2)
+ TEST1("lh", i, reg_val1);
+
+ for (i = 0; i < N*s2; i = i+2)
+ TEST1("lh", i, reg_val2);
+
+ /* lhu */
+ for (i = 0; i < N*s1; i = i+2)
+ TEST1("lhu", i, reg_val1);
+
+ for (i = 0; i < N*s2; i = i+2)
+ TEST1("lhu", i, reg_val2);
+
+ /* lw */
+ for (i = 0; i < N*s1; i = i+4)
+ TEST1("lw", i, reg_val1);
+
+ for (i = 0; i < N*s2; i = i+4)
+ TEST1("lw", i, reg_val2);
+
+ /* lwl */
+ for (i = 0; i < N*s1; i++)
+ TEST1("lwl", i, reg_val1);
+
+ for (i = 0; i < N*s2; i++)
+ TEST1("lwl", i, reg_val2);
+
+ /* lwr */
+ for (i = 0; i < N*s1; i++)
+ TEST1("lwr", i, reg_val1);
+
+ for (i = 0; i < N*s2; i++)
+ TEST1("lwr", i, reg_val2);
+
+ /* lwu */
+ for (i = 0; i < N*s1; i = i+4)
+ TEST1("lwu", i, reg_val1);
+
+ for (i = 0; i < N*s2; i = i+4)
+ TEST1("lwu", i, reg_val2);
+
+ /**********************************************************************/
+ /*-------------------------------STORE--------------------------------*/
+ /**********************************************************************/
+ init_reg_val_zero();
+ /* sb */
+ for (i = 0; i < (N-1)*s2; i++)
+ TEST2("sb", i);
+
+ init_reg_val_zero();
+ /* sd */
+ for (i = 0; i < (N-1)*s2; i = i+8)
+ TEST2("sd", i);
+
+ init_reg_val_zero();
+ /* sdl */
+ for (i = 0; i < (N-1)*s2; i++)
+ TEST2("sdl", i);
+
+ init_reg_val_zero();
+ /* sdr */
+ for (i = 8; i < (N-1)*s2; i++)
+ TEST2("sdr", i);
+
+ init_reg_val_zero();
+ /* sh */
+ for (i = 0; i < (N-1)*s2; i = i+2)
+ TEST2("sh", i);
+
+ init_reg_val_zero();
+ /* sw */
+ for (i = 0; i < (N-1)*s2; i = i+4)
+ TEST2("sw", i);
+
+ init_reg_val_zero();
+ /* swl */
+ for (i = 4; i < (N-1)*s2; i++)
+ TEST2("swl", i);
+
+ init_reg_val_zero();
+ /* swr */
+ for (i = 4; i < (N-1)*s2; i++)
+ TEST2("swr", i);
+
+ return 0;
+}
Added: trunk/none/tests/mips64/test_block_size.c (+71 -0)
===================================================================
--- trunk/none/tests/mips64/test_block_size.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/test_block_size.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,71 @@
+#include <stdio.h>
+
+__attribute__((noinline)) int test_block_size1 ()
+{
+ int result = 1;
+ __asm__ __volatile__(
+ ".set noreorder" "\n\t"
+ ".set nomacro" "\n\t"
+ "b begin1" "\n\t"
+ "nop" "\n\t"
+ "begin1:" "\n\t"
+ ".rept 56" "\n\t"
+ ".word 0" "\n\t"
+ ".endr" "\n\t"
+ "li $a0, 0" "\n\t"
+ "j end1" "\n\t"
+ "nop" "\n\t"
+ "b label1" "\n\t"
+ "nop" "\n\t"
+ "label1:" "\n\t"
+ "li $a0, 1" "\n\t"
+ "end1:" "\n\t"
+ "move %0, $a0" "\n\t"
+ ".set reorder" "\n\t"
+ ".set macro" "\n\t"
+ : /* out */ "=r" (result)
+ : /* in */
+ : /* trash */ "a0");
+ return result;
+}
+
+__attribute__((noinline)) int test_block_size2 ()
+{
+ int result = 1;
+ __asm__ __volatile__(
+ ".set noreorder" "\n\t"
+ ".set nomacro" "\n\t"
+ "b begin2" "\n\t"
+ "nop" "\n\t"
+ "begin2:" "\n\t"
+ ".rept 58" "\n\t"
+ ".word 0" "\n\t"
+ ".endr" "\n\t"
+ "li $a0, 1" "\n\t"
+ "j end2" "\n\t"
+ "li $a0, 0" "\n\t"
+ "end2:" "\n\t"
+ "move %0, $a0" "\n\t"
+ ".set reorder" "\n\t"
+ ".set macro" "\n\t"
+ : /* out */ "=r" (result)
+ : /* in */
+ : /* trash */ "a0");
+ return result;
+}
+
+int main ()
+{
+ /*******************TEST1*******************/
+ if (test_block_size1() == 0)
+ printf("test1 - PASS\n");
+ else
+ printf("test1 - FAIL\n");
+
+ /*******************TEST2*******************/
+ if (test_block_size2() == 0)
+ printf("test2 - PASS\n");
+ else
+ printf("test2 - FAIL\n");
+ return 0;
+}
Added: trunk/none/tests/mips64/round.c (+163 -0)
===================================================================
--- trunk/none/tests/mips64/round.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/round.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,163 @@
+#include <stdio.h>
+#include "rounding_mode.h"
+#include "macro_fpu.h"
+
+int directedRoundingMode(flt_dir_op_t op) {
+ int fd_w = 0;
+ long long int fd_l = 0;
+ int i;
+ for (i = 0; i < MAX_ARR; i++) {
+ switch(op) {
+ case CEILWS:
+ UNOPfw("ceil.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case CEILWD:
+ UNOPdw("ceil.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case FLOORWS:
+ UNOPfw("floor.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case FLOORWD:
+ UNOPdw("floor.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case ROUNDWS:
+ UNOPfw("round.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case ROUNDWD:
+ UNOPdw("round.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case TRUNCWS:
+ UNOPfw("trunc.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case TRUNCWD:
+ UNOPdw("trunc.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case CEILLS:
+ UNOPsl("ceil.l.s");
+ printf("%s %lld %f\n", flt_dir_op_names[op], fd_l, fs_f[i]);
+ break;
+ case CEILLD:
+ UNOPdl("ceil.l.d");
+ printf("%s %lld %lf\n", flt_dir_op_names[op], fd_l, fs_d[i]);
+ break;
+ case FLOORLS:
+ UNOPsl("floor.l.s");
+ printf("%s %lld %f\n", flt_dir_op_names[op], fd_l, fs_f[i]);
+ break;
+ case FLOORLD:
+ UNOPdl("floor.l.d");
+ printf("%s %lld %lf\n", flt_dir_op_names[op], fd_l, fs_d[i]);
+ break;
+ case ROUNDLS:
+ UNOPsl("round.l.s");
+ printf("%s %lld %f\n", flt_dir_op_names[op], fd_l, fs_f[i]);
+ break;
+ case ROUNDLD:
+ UNOPdl("round.l.d");
+ printf("%s %lld %lf\n", flt_dir_op_names[op], fd_l, fs_d[i]);
+ break;
+ case TRUNCLS:
+ UNOPsl("trunc.l.s");
+ printf("%s %lld %f\n", flt_dir_op_names[op], fd_l, fs_f[i]);
+ break;
+ case TRUNCLD:
+ UNOPdl("trunc.l.d");
+ printf("%s %lld %lf\n", flt_dir_op_names[op], fd_l, fs_d[i]);
+ break;
+ default:
+ printf("error\n");
+ break;
+ }
+ }
+ return 0;
+}
+
+int FCSRRoundingMode(flt_round_op_t op1)
+{
+ double fd_d = 0;
+ float fd_f = 0;
+ int fd_w = 0;
+ long long int fd_l = 0;
+ int i;
+ round_mode_t rm;
+ for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++) {
+ set_rounding_mode(rm);
+ printf("roundig mode: %s\n", round_mode_name[rm]);
+ for (i = 0; i < MAX_ARR; i++) {
+ set_rounding_mode(rm);
+ switch(op1) {
+ case CVTDS:
+ UNOPfd("cvt.d.s");
+ printf("%s %lf %lf\n", flt_round_op_names[op1], fd_d, fs_f[i]);
+ break;
+ case CVTDW:
+ UNOPwd("cvt.d.w");
+ printf("%s %lf %d\n", flt_round_op_names[op1], fd_d, fs_w[i]);
+ break;
+ case CVTSD:
+ UNOPdf("cvt.s.d");
+ printf("%s %f %lf\n", flt_round_op_names[op1], fd_f, fs_d[i]);
+ break;
+ case CVTSW:
+ UNOPwf("cvt.s.w");
+ printf("%s %f %d\n", flt_round_op_names[op1], fd_f, fs_w[i]);
+ break;
+ case CVTWS:
+ UNOPfw("cvt.w.s");
+ printf("%s %d %f\n", flt_round_op_names[op1], fd_w, fs_f[i]);
+ break;
+ case CVTWD:
+ UNOPdw("cvt.w.d");
+ printf("%s %d %lf\n", flt_round_op_names[op1], fd_w, fs_d[i]);
+ break;
+ case CVTDL:
+ UNOPld("cvt.d.l");
+ printf("%s %lf %ld\n", flt_round_op_names[op1], fd_d, fs_l[i]);
+ break;
+ case CVTLS:
+ UNOPsl("cvt.l.s");
+ printf("%s %lld %f\n", flt_round_op_names[op1], fd_l, fs_f[i]);
+ break;
+ case CVTLD:
+ UNOPdl("cvt.l.d");
+ printf("%s %lld %lf\n", flt_round_op_names[op1], fd_l, fs_d[i]);
+ break;
+ case CVTSL:
+ UNOPls("cvt.s.l");
+ printf("%s %f %ld\n", flt_round_op_names[op1], fd_f, fs_l[i]);
+ break;
+ default:
+ printf("error\n");
+ break;
+ }
+ }
+ }
+ return 0;
+}
+
+int main()
+{
+ flt_dir_op_t op;
+ flt_round_op_t op1;
+
+ printf("-------------------------- %s --------------------------\n",
+ "test FPU Conversion Operations Using a Directed Rounding Mode");
+ for (op = CEILWS; op <= TRUNCLS; op++) {
+ directedRoundingMode(op);
+ }
+
+ printf("-------------------------- %s --------------------------\n",
+ "test FPU Conversion Operations Using the FCSR Rounding Mode");
+ for (op1 = CVTDS; op1 <= CVTSL; op1++) {
+ FCSRRoundingMode(op1);
+ }
+ return 0;
+}
Added: trunk/none/tests/mips64/branch_and_jump_instructions.c (+352 -0)
===================================================================
--- trunk/none/tests/mips64/branch_and_jump_instructions.c 2013-05-26 22:09:20 +01:00 (rev 13409)
+++ trunk/none/tests/mips64/branch_and_jump_instructions.c 2013-05-28 17:51:27 +01:00 (rev 13410)
@@ -0,0 +1,352 @@
+#include <stdio.h>
+#include "const.h"
+
+#define TEST1(RSval, RD) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "move $"#RD", %1" "\n\t" \
+ "b end"#RD "\n\t" \
+ "nop" "\n\t" \
+ "daddi $"#RD", $"#RD", 5" "\n\t" \
+ "end"#RD":" "\n\t" \
+ "daddi $"#RD", $"#RD", 1" "\n\t" \
+ "move %0, $"#RD "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=r" (out) \
+ : "r" (RSval) \
+ : #RD \
+ ); \
+ printf("B :: 0x%llx, RSval: 0x%llx\n", \
+ out, (long long) RSval); \
+}
+
+#define TEST2(RSval, RD) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "move $"#RD", %1" "\n\t" \
+ "bal end1"#RD "\n\t" \
+ "nop" "\n\t" \
+ "daddi $"#RD", $"#RD", 5" "\n\t" \
+ "b r_end"#RD "\n\t" \
+ "nop" "\n\t" \
+ "end1"#RD":" "\n\t" \
+ "daddi $"#RD", $"#RD", 1" "\n\t" \
+ "jr $ra" "\n\t" \
+ "nop" "\n\t" \
+ "r_end"#RD":" "\n\t" \
+ "move %0, $"#RD "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=r" (out) \
+ : "r" (RSval) \
+ : #RD, "ra" \
+ ); \
+ printf("B BAL JR :: 0x%llx, RSval: 0x%llx\n", \
+ out, (long long) RSval); \
+}
+
+#define TEST2a(RSval, RD) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "move $"#RD", %1" "\n\t" \
+ "bal end12"#RD "\n\t" \
+ "nop" "\n\t" \
+ "daddi $"#RD", $"#RD", 5" "\n\t" \
+ "move $t9, $ra" "\n\t" \
+ "jr $t9" "\n\t" \
+ "nop" "\n\t" \
+ "daddi $"#RD", $"#RD", 1" "\n\t" \
+ "end12"#RD":" "\n\t" \
+ "daddi $"#RD", $"#RD", 1" "\n\t" \
+ "move $t9, $ra" "\n\t" \
+ "jal $t9" "\n\t" \
+ "nop" "\n\t" \
+ "move %0, $"#RD "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=r" (out) \
+ : "r" (RSval) \
+ : #RD, "t9", "ra" \
+ ); \
+ printf("BAL JR JAL :: 0x%llx, RSval: 0x%llx\n", \
+ out, (long long) RSval); \
+}
+
+#define TEST2b(RSval, RD) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" \
+ "move $"#RD", %1" "\n\t" \
+ "bal end13"#RD "\n\t" \
+ "nop" "\n\t" \
+ "daddi $"#RD", $"#RD", 5" "\n\t" \
+ "move $t9, $t0" "\n\t" \
+ "j $t9" "\n\t" \
+ "nop" "\n\t" \
+ "daddi $"#RD", $"#RD", 1" "\n\t" \
+ "end13"#RD":" "\n\t" \
+ "daddi $"#RD", $"#RD", 1" "\n\t" \
+ "move $t9, $ra" "\n\t" \
+ "jalr $t0, $t9" "\n\t" \
+ "nop" "\n\t" \
+ "move %0, $"#RD "\n\t" \
+ ".set reorder" "\n\t" \
+ : "=r" (out) \
+ : "r" (RSval) \
+ : #RD, "t0", "t9", "ra" \
+ ); \
+ printf("BAL JR JAL :: 0x%llx, RSval: 0x%llx\n", \
+ out, (long long) RSval); \
+}
+
+#define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ __volatile__( \
+ ".set noreorder" "\n\t" ...
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