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From: <sv...@va...> - 2012-10-29 21:28:13
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weidendo 2012-10-29 21:28:05 +0000 (Mon, 29 Oct 2012)
New Revision: 13093
Log:
Use always_inline attribute also in Callgrinds simulator
Modified files:
trunk/callgrind/sim.c
Modified: trunk/callgrind/sim.c (+14 -6)
===================================================================
--- trunk/callgrind/sim.c 2012-10-29 21:28:03 +00:00 (rev 13092)
+++ trunk/callgrind/sim.c 2012-10-29 21:28:05 +00:00 (rev 13093)
@@ -227,18 +227,23 @@
/*------------------------------------------------------------*/
-/*--- Write Through Cache Simulation ---*/
+/*--- Simple Cache Simulation ---*/
/*------------------------------------------------------------*/
/*
- * Simple model: L1 & LL Write Through
- * Does not distinguish among read and write references
+ * Model: single inclusive, 2-level cache hierarchy (L1/LL)
+ * with write-allocate
*
+ * For simple cache hit/miss counts, we do not have to
+ * maintain the dirty state of lines (no need to distinguish
+ * read/write references), and the resulting counts are the
+ * same for write-through and write-back caches.
+ *
* Simulator functions:
* CacheModelResult cachesim_I1_ref(Addr a, UChar size)
* CacheModelResult cachesim_D1_ref(Addr a, UChar size)
*/
-
+__attribute__((always_inline))
static __inline__
CacheResult cachesim_setref(cache_t2* c, UInt set_no, UWord tag)
{
@@ -274,7 +279,9 @@
return Miss;
}
-static CacheResult cachesim_ref(cache_t2* c, Addr a, UChar size)
+__attribute__((always_inline))
+static __inline__
+CacheResult cachesim_ref(cache_t2* c, Addr a, UChar size)
{
UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
@@ -338,6 +345,7 @@
* this cache line (CACHELINE_DIRTY = 1). By OR'ing the reference
* type (Read/Write), the line gets dirty on a write.
*/
+__attribute__((always_inline))
static __inline__
CacheResult cachesim_setref_wb(cache_t2* c, RefType ref, UInt set_no, UWord tag)
{
@@ -376,7 +384,7 @@
return (tmp_tag & CACHELINE_DIRTY) ? MissDirty : Miss;
}
-
+__attribute__((always_inline))
static __inline__
CacheResult cachesim_ref_wb(cache_t2* c, RefType ref, Addr a, UChar size)
{
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