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From: <sv...@va...> - 2012-06-11 21:55:10
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sewardj 2012-06-11 22:54:58 +0100 (Mon, 11 Jun 2012)
New Revision: 2378
Log:
16-bit Thumb PUSH and POP: fix incorrect assertions.
Modified files:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c (+6 -2)
===================================================================
--- trunk/priv/guest_arm_toIR.c 2012-06-07 17:52:41 +01:00 (rev 2377)
+++ trunk/priv/guest_arm_toIR.c 2012-06-11 22:54:58 +01:00 (rev 2378)
@@ -15224,6 +15224,8 @@
UInt regList = INSN0(7,0);
if (bitR) regList |= (1 << 14);
+ /* At least one register must be transferred, else result is
+ UNPREDICTABLE. */
if (regList != 0) {
/* Since we can't generate a guaranteed non-trapping IR
sequence, (1) jump over the insn if it is gated false, and
@@ -15238,7 +15240,7 @@
if ((regList & (1 << i)) != 0)
nRegs++;
}
- vassert(nRegs >= 1 && nRegs <= 8);
+ vassert(nRegs >= 1 && nRegs <= 9);
/* Move SP down first of all, so we're "covered". And don't
mess with its alignment. */
@@ -15276,6 +15278,8 @@
UInt bitR = INSN0(8,8);
UInt regList = INSN0(7,0);
+ /* At least one register must be transferred, else result is
+ UNPREDICTABLE. */
if (regList != 0 || bitR) {
/* Since we can't generate a guaranteed non-trapping IR
sequence, (1) jump over the insn if it is gated false, and
@@ -15290,7 +15294,7 @@
if ((regList & (1 << i)) != 0)
nRegs++;
}
- vassert(nRegs >= 0 && nRegs <= 7);
+ vassert(nRegs >= 0 && nRegs <= 8);
vassert(bitR == 0 || bitR == 1);
IRTemp oldSP = newTemp(Ity_I32);
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