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From: <sv...@va...> - 2012-06-07 08:51:14
|
sewardj 2012-06-07 09:51:02 +0100 (Thu, 07 Jun 2012)
New Revision: 2375
Log:
Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic,
mip...@rt..., Bug 270777.
VEX: changes to existing files.
Modified files:
trunk/Makefile-gcc
trunk/Makefile-icc
trunk/auxprogs/genoffsets.c
trunk/priv/main_main.c
trunk/pub/libvex.h
trunk/pub/libvex_basictypes.h
Modified: trunk/Makefile-icc (+23 -1)
===================================================================
--- trunk/Makefile-icc 2012-06-06 13:53:14 +01:00 (rev 2374)
+++ trunk/Makefile-icc 2012-06-07 09:51:02 +01:00 (rev 2375)
@@ -9,12 +9,14 @@
pub/libvex_guest_arm.h \
pub/libvex_guest_ppc32.h \
pub/libvex_guest_ppc64.h \
+ pub/libvex_guest_mips.h \
pub/libvex_guest_offsets.h
PRIV_HEADERS = priv/host-x86/hdefs.h \
priv/host-amd64/hdefs.h \
priv/host-arm/hdefs.h \
priv/host-ppc/hdefs.h \
+ priv/host-mips/hdefs.h \
priv/host-generic/h_generic_regs.h \
priv/host-generic/h_generic_simd64.h \
priv/main/vex_globals.h \
@@ -25,6 +27,7 @@
priv/guest-amd64/gdefs.h \
priv/guest-arm/gdefs.h \
priv/guest-ppc/gdefs.h \
+ priv/guest-mips/gdefs.h \
priv/ir/irmatch.h \
priv/ir/iropt.h
@@ -42,6 +45,7 @@
priv/host-amd64/isel.o \
priv/host-arm/isel.o \
priv/host-ppc/isel.o \
+ priv/host-mips/isel.o \
priv/host-generic/h_generic_regs.o \
priv/host-generic/h_generic_simd64.o \
priv/host-generic/reg_alloc2.o \
@@ -51,10 +55,12 @@
priv/guest-amd64/ghelpers.o \
priv/guest-arm/ghelpers.o \
priv/guest-ppc/ghelpers.o \
+ priv/guest-mips/ghelpers.o \
priv/guest-x86/toIR.o \
priv/guest-amd64/toIR.o \
priv/guest-arm/toIR.o \
- priv/guest-ppc/toIR.o
+ priv/guest-ppc/toIR.o \
+ priv/guest-mips/toIR.o
PUB_INCLUDES = -Ipub
@@ -170,6 +176,10 @@
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host-ppc/hdefs.o \
-c priv/host-ppc/hdefs.c
+priv/host-mips/hdefs.o: $(ALL_HEADERS) priv/host-mips/hdefs.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host-mips/hdefs.o \
+ -c priv/host-mips/hdefs.c
+
priv/host-x86/isel.o: $(ALL_HEADERS) priv/host-x86/isel.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host-x86/isel.o \
-c priv/host-x86/isel.c
@@ -186,6 +196,10 @@
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host-ppc/isel.o \
-c priv/host-ppc/isel.c
+priv/host-mips/isel.o: $(ALL_HEADERS) priv/host-mips/isel.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host-mips/isel.o \
+ -c priv/host-mips/isel.c
+
priv/host-generic/h_generic_regs.o: $(ALL_HEADERS) priv/host-generic/h_generic_regs.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host-generic/h_generic_regs.o \
-c priv/host-generic/h_generic_regs.c
@@ -237,3 +251,11 @@
priv/guest-ppc/toIR.o: $(ALL_HEADERS) priv/guest-ppc/toIR.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest-ppc/toIR.o \
-c priv/guest-ppc/toIR.c
+
+priv/guest-mips/ghelpers.o: $(ALL_HEADERS) priv/guest-mips/ghelpers.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest-mips/ghelpers.o \
+ -c priv/guest-mips/ghelpers.c
+
+priv/guest-mips/toIR.o: $(ALL_HEADERS) priv/guest-mips/toIR.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest-mips/toIR.o \
+ -c priv/guest-mips/toIR.c
Modified: trunk/Makefile-gcc (+30 -1)
===================================================================
--- trunk/Makefile-gcc 2012-06-06 13:53:14 +01:00 (rev 2374)
+++ trunk/Makefile-gcc 2012-06-07 09:51:02 +01:00 (rev 2375)
@@ -11,6 +11,7 @@
pub/libvex_guest_ppc64.h \
pub/libvex_guest_s390x.h \
pub/libvex_s390x_common.h \
+ pub/libvex_guest_mips.h \
pub/libvex_guest_offsets.h
PRIV_HEADERS = priv/host_x86_defs.h \
@@ -19,6 +20,7 @@
priv/host_ppc_defs.h \
priv/host_s390_defs.h \
priv/host_s390_disasm.h \
+ priv/host_mips_defs.h \
priv/host_generic_regs.h \
priv/host_generic_simd64.h \
priv/host_generic_simd128.h \
@@ -30,6 +32,7 @@
priv/guest_amd64_defs.h \
priv/guest_arm_defs.h \
priv/guest_ppc_defs.h \
+ priv/guest_mips_defs.h \
priv/ir_match.h \
priv/ir_opt.h
@@ -44,12 +47,14 @@
priv/host_arm_defs.o \
priv/host_ppc_defs.o \
priv/host_s390_defs.o \
+ priv/host_mips_defs.o \
priv/host_x86_isel.o \
priv/host_amd64_isel.o \
priv/host_arm_isel.o \
priv/host_ppc_isel.o \
priv/host_s390_isel.o \
priv/host_s390_disasm.o \
+ priv/host_mips_isel.o \
priv/host_generic_regs.o \
priv/host_generic_simd64.o \
priv/host_generic_simd128.o \
@@ -61,11 +66,13 @@
priv/guest_arm_helpers.o \
priv/guest_ppc_helpers.o \
priv/guest_s390_helpers.o \
+ priv/guest_mips_helpers.o \
priv/guest_x86_toIR.o \
priv/guest_amd64_toIR.o \
priv/guest_arm_toIR.o \
priv/guest_ppc_toIR.o \
- priv/guest_s390_toIR.o
+ priv/guest_s390_toIR.o \
+ priv/guest_mips_toIR.o
PUB_INCLUDES = -Ipub
@@ -151,6 +158,12 @@
if [ ! -f TAG-ppc64-linux ] ; then rm -f $(LIB_OBJS) TAG-* libvex.a ; fi
touch TAG-ppc64-linux
+libvex-mips-linux.a: TAG-mips32-linux libvex.a
+ mv -f libvex.a libvex-mips32-linux.a
+TAG-mips-linux:
+ if [ ! -f TAG-mips32-linux ] ; then rm -f $(LIB_OBJS) TAG-* libvex.a ; fi
+ touch TAG-mips32-linux
+
libvex-ppc32-aix5.a: TAG-ppc32-aix5 libvex.a
mv -f libvex.a libvex-ppc32-aix5.a
TAG-ppc32-aix5:
@@ -258,6 +271,10 @@
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_s390_defs.o \
-c priv/host_s390_defs.c
+priv/host_mips_defs.o: $(ALL_HEADERS) priv/host_mips_defs.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_mips_defs.o \
+ -c priv/host_mips_defs.c
+
priv/host_x86_isel.o: $(ALL_HEADERS) priv/host_x86_isel.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_x86_isel.o \
-c priv/host_x86_isel.c
@@ -278,6 +295,10 @@
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_s390_isel.o \
-c priv/host_s390_isel.c
+priv/host_mips_isel.o: $(ALL_HEADERS) priv/host_mips_isel.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_mips_isel.o \
+ -c priv/host_mips_isel.c
+
priv/host_generic_regs.o: $(ALL_HEADERS) priv/host_generic_regs.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_regs.o \
-c priv/host_generic_regs.c
@@ -345,3 +366,11 @@
priv/host_s390_disasm.o: $(ALL_HEADERS) priv/host_s390_disasm.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_s390_disasm.o \
-c priv/host_s390_disasm.c
+
+priv/guest_mips_helpers.o: $(ALL_HEADERS) priv/guest_mips_helpers.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_helpers.o \
+ -c priv/guest_mips_helpers.c
+
+priv/guest_mips_toIR.o: $(ALL_HEADERS) priv/guest_mips_toIR.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_toIR.o \
+ -c priv/guest_mips_toIR.c
Modified: trunk/priv/main_main.c (+75 -6)
===================================================================
--- trunk/priv/main_main.c 2012-06-06 13:53:14 +01:00 (rev 2374)
+++ trunk/priv/main_main.c 2012-06-07 09:51:02 +01:00 (rev 2375)
@@ -41,6 +41,7 @@
#include "libvex_guest_ppc32.h"
#include "libvex_guest_ppc64.h"
#include "libvex_guest_s390x.h"
+#include "libvex_guest_mips32.h"
#include "main_globals.h"
#include "main_util.h"
@@ -52,6 +53,7 @@
#include "host_ppc_defs.h"
#include "host_arm_defs.h"
#include "host_s390_defs.h"
+#include "host_mips_defs.h"
#include "guest_generic_bb_to_IR.h"
#include "guest_x86_defs.h"
@@ -59,6 +61,7 @@
#include "guest_arm_defs.h"
#include "guest_ppc_defs.h"
#include "guest_s390_defs.h"
+#include "guest_mips_defs.h"
#include "host_generic_simd128.h"
@@ -395,6 +398,30 @@
vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps));
break;
+ case VexArchMIPS32:
+ mode64 = False;
+ getAllocableRegs_MIPS ( &n_available_real_regs,
+ &available_real_regs, mode64 );
+ isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_MIPSInstr;
+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_MIPSInstr;
+ mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_MIPSInstr;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_MIPS;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_MIPS;
+ ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr;
+ ppReg = (void(*)(HReg)) ppHRegMIPS;
+ iselSB = iselSB_MIPS;
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
+ emit_MIPSInstr;
+#if defined(VKI_LITTLE_ENDIAN)
+ host_is_bigendian = False;
+#elif defined(VKI_BIG_ENDIAN)
+ host_is_bigendian = True;
+#endif
+ host_word_type = Ity_I32;
+ vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps));
+ break;
+
default:
vpanic("LibVEX_Translate: unsupported host insn set");
}
@@ -523,6 +550,26 @@
vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4);
break;
+ case VexArchMIPS32:
+ preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_MIPS;
+ specHelper = guest_mips32_spechelper;
+ guest_sizeB = sizeof(VexGuestMIPS32State);
+ guest_word_type = Ity_I32;
+ guest_layout = &mips32Guest_layout;
+ offB_TISTART = offsetof(VexGuestMIPS32State,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestMIPS32State,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC);
+ szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR);
+ vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps));
+ vassert(0 == sizeof(VexGuestMIPS32State) % 16);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TISTART) == 4);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TILEN ) == 4);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4);
+ break;
+
default:
vpanic("LibVEX_Translate: unsupported guest insn set");
}
@@ -845,6 +892,10 @@
return chainXDirect_PPC(place_to_chain,
disp_cp_chain_me_EXPECTED,
place_to_jump_to, True/*mode64*/);
+ case VexArchMIPS32:
+ return chainXDirect_MIPS(place_to_chain,
+ disp_cp_chain_me_EXPECTED,
+ place_to_jump_to, False/*!mode64*/);
default:
vassert(0);
}
@@ -878,6 +929,10 @@
return unchainXDirect_PPC(place_to_unchain,
place_to_jump_to_EXPECTED,
disp_cp_chain_me, True/*mode64*/);
+ case VexArchMIPS32:
+ return unchainXDirect_MIPS(place_to_unchain,
+ place_to_jump_to_EXPECTED,
+ disp_cp_chain_me, False/*!mode64*/);
default:
vassert(0);
}
@@ -904,6 +959,8 @@
case VexArchPPC32:
case VexArchPPC64:
cached = evCheckSzB_PPC(); break;
+ case VexArchMIPS32:
+ cached = evCheckSzB_MIPS(); break;
default:
vassert(0);
}
@@ -931,6 +988,9 @@
case VexArchPPC64:
return patchProfInc_PPC(place_to_patch,
location_of_counter, True/*mode64*/);
+ case VexArchMIPS32:
+ return patchProfInc_MIPS(place_to_patch,
+ location_of_counter, False/*!mode64*/);
default:
vassert(0);
}
@@ -983,6 +1043,7 @@
case VexArchPPC32: return "PPC32";
case VexArchPPC64: return "PPC64";
case VexArchS390X: return "S390X";
+ case VexArchMIPS32: return "MIPS32";
default: return "VexArch???";
}
}
@@ -1217,16 +1278,24 @@
return buf;
}
+static HChar* show_hwcaps_mips32 ( UInt hwcaps )
+{
+ if (hwcaps == 0x00010000) return "MIPS-baseline";
+ if (hwcaps == 0x00020000) return "Broadcom-baseline";
+ return NULL;
+}
+
/* ---- */
static HChar* show_hwcaps ( VexArch arch, UInt hwcaps )
{
switch (arch) {
- case VexArchX86: return show_hwcaps_x86(hwcaps);
- case VexArchAMD64: return show_hwcaps_amd64(hwcaps);
- case VexArchPPC32: return show_hwcaps_ppc32(hwcaps);
- case VexArchPPC64: return show_hwcaps_ppc64(hwcaps);
- case VexArchARM: return show_hwcaps_arm(hwcaps);
- case VexArchS390X: return show_hwcaps_s390x(hwcaps);
+ case VexArchX86: return show_hwcaps_x86(hwcaps);
+ case VexArchAMD64: return show_hwcaps_amd64(hwcaps);
+ case VexArchPPC32: return show_hwcaps_ppc32(hwcaps);
+ case VexArchPPC64: return show_hwcaps_ppc64(hwcaps);
+ case VexArchARM: return show_hwcaps_arm(hwcaps);
+ case VexArchS390X: return show_hwcaps_s390x(hwcaps);
+ case VexArchMIPS32: return show_hwcaps_mips32(hwcaps);
default: return NULL;
}
}
Modified: trunk/pub/libvex.h (+18 -1)
===================================================================
--- trunk/pub/libvex.h 2012-06-06 13:53:14 +01:00 (rev 2374)
+++ trunk/pub/libvex.h 2012-06-07 09:51:02 +01:00 (rev 2375)
@@ -57,7 +57,8 @@
VexArchARM,
VexArchPPC32,
VexArchPPC64,
- VexArchS390X
+ VexArchS390X,
+ VexArchMIPS32
}
VexArch;
@@ -154,6 +155,22 @@
/* Get an ARM architecure level from HWCAPS */
#define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f)
+/* MIPS baseline capability */
+/* Assigned Company values for bits 23:16 of the PRId Register
+ (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
+ MTI, the PRId register is defined in this (backwards compatible)
+ way:
+
+ +----------------+----------------+----------------+----------------+
+ | Company Options| Company ID | Processor ID | Revision |
+ +----------------+----------------+----------------+----------------+
+ 31 24 23 16 15 8 7
+
+*/
+
+#define VEX_PRID_COMP_MIPS 0x00010000
+#define VEX_PRID_COMP_BROADCOM 0x00020000
+
/* These return statically allocated strings. */
extern const HChar* LibVEX_ppVexArch ( VexArch );
Modified: trunk/pub/libvex_basictypes.h (+4 -0)
===================================================================
--- trunk/pub/libvex_basictypes.h 2012-06-06 13:53:14 +01:00 (rev 2374)
+++ trunk/pub/libvex_basictypes.h 2012-06-07 09:51:02 +01:00 (rev 2375)
@@ -174,6 +174,10 @@
# define VEX_HOST_WORDSIZE 8
# define VEX_REGPARM(_n) /* */
+#elif defined(__mips__)
+# define VEX_HOST_WORDSIZE 4
+# define VEX_REGPARM(_n) /* */
+
#else
# error "Vex: Fatal: Can't establish the host architecture"
#endif
Modified: trunk/auxprogs/genoffsets.c (+38 -0)
===================================================================
--- trunk/auxprogs/genoffsets.c 2012-06-06 13:53:14 +01:00 (rev 2374)
+++ trunk/auxprogs/genoffsets.c 2012-06-07 09:51:02 +01:00 (rev 2375)
@@ -52,6 +52,7 @@
#include "../pub/libvex_guest_ppc64.h"
#include "../pub/libvex_guest_arm.h"
#include "../pub/libvex_guest_s390x.h"
+#include "../pub/libvex_guest_mips32.h"
#define VG_STRINGIFZ(__str) #__str
#define VG_STRINGIFY(__str) VG_STRINGIFZ(__str)
@@ -173,6 +174,43 @@
GENOFFSET(S390X,s390x,CC_DEP1);
GENOFFSET(S390X,s390x,CC_DEP2);
GENOFFSET(S390X,s390x,CC_NDEP);
+
+ // MIPS32
+ GENOFFSET(MIPS32,mips32,r0);
+ GENOFFSET(MIPS32,mips32,r1);
+ GENOFFSET(MIPS32,mips32,r2);
+ GENOFFSET(MIPS32,mips32,r3);
+ GENOFFSET(MIPS32,mips32,r4);
+ GENOFFSET(MIPS32,mips32,r5);
+ GENOFFSET(MIPS32,mips32,r6);
+ GENOFFSET(MIPS32,mips32,r7);
+ GENOFFSET(MIPS32,mips32,r8);
+ GENOFFSET(MIPS32,mips32,r9);
+ GENOFFSET(MIPS32,mips32,r10);
+ GENOFFSET(MIPS32,mips32,r11);
+ GENOFFSET(MIPS32,mips32,r12);
+ GENOFFSET(MIPS32,mips32,r13);
+ GENOFFSET(MIPS32,mips32,r14);
+ GENOFFSET(MIPS32,mips32,r15);
+ GENOFFSET(MIPS32,mips32,r15);
+ GENOFFSET(MIPS32,mips32,r17);
+ GENOFFSET(MIPS32,mips32,r18);
+ GENOFFSET(MIPS32,mips32,r19);
+ GENOFFSET(MIPS32,mips32,r20);
+ GENOFFSET(MIPS32,mips32,r21);
+ GENOFFSET(MIPS32,mips32,r22);
+ GENOFFSET(MIPS32,mips32,r23);
+ GENOFFSET(MIPS32,mips32,r24);
+ GENOFFSET(MIPS32,mips32,r25);
+ GENOFFSET(MIPS32,mips32,r26);
+ GENOFFSET(MIPS32,mips32,r27);
+ GENOFFSET(MIPS32,mips32,r28);
+ GENOFFSET(MIPS32,mips32,r29);
+ GENOFFSET(MIPS32,mips32,r30);
+ GENOFFSET(MIPS32,mips32,r31);
+ GENOFFSET(MIPS32,mips32,PC);
+ GENOFFSET(MIPS32,mips32,HI);
+ GENOFFSET(MIPS32,mips32,LO);
}
/*--------------------------------------------------------------------*/
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