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From: <sv...@va...> - 2012-05-22 23:12:21
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sewardj 2012-05-23 00:12:13 +0100 (Wed, 23 May 2012)
New Revision: 2339
Log:
Implement
VMOVQ xmm1, r64 = VEX.128.66.0F.W1 7E /r (reg case only)
If this is documented in the Intel manuals, I can't find it.
GNU binutils and GDB seem to have heard of it, though.
Modified files:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c (+15 -1)
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2012-05-22 11:48:13 +01:00 (rev 2338)
+++ trunk/priv/guest_amd64_toIR.c 2012-05-23 00:12:13 -23:00 (rev 2339)
@@ -20374,7 +20374,7 @@
are wrong. They seem to imply it is a store when in fact I
think it is a load. Also it's unclear whether this is W0, W1
or WIG. */
- /* VMOVQ xmm2/m64, xmm1 = VEX.128.F3.0F.W0 */
+ /* VMOVQ xmm2/m64, xmm1 = VEX.128.F3.0F.W0 7E /r */
if (haveF3no66noF2(pfx)
&& 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
vassert(sz == 4); /* even tho we are transferring 8, not 4. */
@@ -20396,6 +20396,20 @@
putYMMRegLane128( rG, 1, mkV128(0) );
goto decode_success;
}
+ /* VMOVQ xmm1, r64 = VEX.128.66.0F.W1 7E /r (reg case only) */
+ /* Moves from G to E, so is a store-form insn */
+ /* Intel docs for this are completely missing, AFAICS */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 1==getRexW(pfx)/*W1*/
+ && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rE = eregOfRexRM(pfx,modrm);
+ DIP("vmovq %s,%s\n", nameXMMReg(rG), nameIReg64(rE));
+ putIReg64(rE, getXMMRegLane64(rG, 0));
+ delta += 1;
+ goto decode_success;
+ }
break;
case 0x7F:
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