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From: <sv...@va...> - 2012-04-04 14:21:06
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sewardj 2012-04-04 15:20:56 +0100 (Wed, 04 Apr 2012)
New Revision: 2275
Log:
ARMin_MFence: implement using ARMv7 insns instead of the legacy mcr-15
instructions.
Modified files:
branches/TCHAIN/priv/host_arm_defs.c
Modified: branches/TCHAIN/priv/host_arm_defs.c (+10 -5)
===================================================================
--- branches/TCHAIN/priv/host_arm_defs.c 2012-04-04 04:47:33 +01:00 (rev 2274)
+++ branches/TCHAIN/priv/host_arm_defs.c 2012-04-04 15:20:56 +01:00 (rev 2275)
@@ -1815,8 +1815,7 @@
}
return;
case ARMin_MFence:
- vex_printf("mfence (mcr 15,0,r0,c7,c10,4; 15,0,r0,c7,c10,5; "
- "15,0,r0,c7,c5,4)");
+ vex_printf("(mfence) dsb sy; dmb sy; isb");
return;
case ARMin_CLREX:
vex_printf("clrex");
@@ -3605,9 +3604,15 @@
goto bad; // FPSCR -> iReg case currently ATC
}
case ARMin_MFence: {
- *p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */
- *p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */
- *p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */
+ // It's not clear (to me) how these relate to the ARMv7
+ // versions, so let's just use the v7 versions as they
+ // are at least well documented.
+ //*p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */
+ //*p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */
+ //*p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */
+ *p++ = 0xF57FF04F; /* DSB sy */
+ *p++ = 0xF57FF05F; /* DMB sy */
+ *p++ = 0xF57FF06F; /* ISB */
goto done;
}
case ARMin_CLREX: {
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