|
From: <sv...@va...> - 2010-10-11 18:57:18
|
Author: sewardj
Date: 2010-10-11 19:57:10 +0100 (Mon, 11 Oct 2010)
New Revision: 2064
Log:
Handle NOP.W (Thumb) and NOP (ARM). Partial fix for #253636.
Add a comment re conditionalisation of Thumb memory barrier insns.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
===================================================================
--- trunk/priv/guest_arm_toIR.c 2010-10-11 18:03:13 UTC (rev 2063)
+++ trunk/priv/guest_arm_toIR.c 2010-10-11 18:57:10 UTC (rev 2064)
@@ -13808,6 +13808,12 @@
}
}
+ /* ------------------- NOP ------------------ */
+ if (0x0320F000 == (insn & 0x0FFFFFFF)) {
+ DIP("nop%s\n", nCC(INSN_COND));
+ goto decode_success;
+ }
+
/* ----------------------------------------------------------- */
/* -- ARMv7 instructions -- */
/* ----------------------------------------------------------- */
@@ -17643,6 +17649,10 @@
/* -------------- v7 barrier insns -------------- */
if (INSN0(15,0) == 0xF3BF && (INSN1(15,0) & 0xFF0F) == 0x8F0F) {
+ /* XXX this isn't really right, is it? The generated IR does
+ them unconditionally. I guess it doesn't matter since it
+ doesn't do any harm to do them even when the guarding
+ condition is false -- it's just a performance loss. */
switch (INSN1(7,4)) {
case 0x4: /* DSB */
stmt( IRStmt_MBE(Imbe_Fence) );
@@ -17661,6 +17671,12 @@
}
}
+ /* ------------------- NOP ------------------ */
+ if (INSN0(15,0) == 0xF3AF && INSN1(15,0) == 0x8000) {
+ DIP("nop\n");
+ goto decode_success;
+ }
+
/* ----------------------------------------------------------- */
/* -- VFP (CP 10, CP 11) instructions (in Thumb mode) -- */
/* ----------------------------------------------------------- */
|