|
From: <sv...@va...> - 2010-08-31 09:32:49
|
Author: sewardj
Date: 2010-08-31 10:32:40 +0100 (Tue, 31 Aug 2010)
New Revision: 2024
Log:
Reduce to 5 the number of available Q (128-bit) registers available
to the allocator, in an attempt to make register allocation a bit
faster on ARM.
Modified:
trunk/priv/host_arm_defs.c
Modified: trunk/priv/host_arm_defs.c
===================================================================
--- trunk/priv/host_arm_defs.c 2010-08-31 09:31:06 UTC (rev 2023)
+++ trunk/priv/host_arm_defs.c 2010-08-31 09:32:40 UTC (rev 2024)
@@ -119,7 +119,7 @@
void getAllocableRegs_ARM ( Int* nregs, HReg** arr )
{
Int i = 0;
- *nregs = 29;
+ *nregs = 26;
*arr = LibVEX_Alloc(*nregs * sizeof(HReg));
// callee saves ones are listed first, since we prefer them
// if they're available
@@ -154,10 +154,11 @@
(*arr)[i++] = hregARM_Q10();
(*arr)[i++] = hregARM_Q11();
(*arr)[i++] = hregARM_Q12();
- (*arr)[i++] = hregARM_Q13();
- (*arr)[i++] = hregARM_Q14();
- (*arr)[i++] = hregARM_Q15();
+ //(*arr)[i++] = hregARM_Q13();
+ //(*arr)[i++] = hregARM_Q14();
+ //(*arr)[i++] = hregARM_Q15();
+
// unavail: r8 as GSP
// r12 'cos we're not sure what it's for
// r13 as SP
|