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From: <sv...@va...> - 2010-08-22 10:29:42
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Author: sewardj
Date: 2010-08-22 11:29:32 +0100 (Sun, 22 Aug 2010)
New Revision: 11275
Log:
Back out a bunch of experimental ARM-Thumb interworking changes. It
appears the core can handle interworking with almost zero changes.
Only known place where it needs special casing is when backing up over
an interrupted syscall, since the encoding of the SVC instruction is
different for ARM vs Thumb.
Modified:
branches/THUMB/coregrind/m_coredump/coredump-elf.c
branches/THUMB/coregrind/m_debugger.c
branches/THUMB/coregrind/m_debuginfo/debuginfo.c
branches/THUMB/coregrind/m_execontext.c
branches/THUMB/coregrind/m_machine.c
branches/THUMB/coregrind/m_main.c
branches/THUMB/coregrind/m_scheduler/scheduler.c
branches/THUMB/coregrind/m_sigframe/sigframe-arm-linux.c
branches/THUMB/coregrind/m_signals.c
branches/THUMB/coregrind/m_translate.c
branches/THUMB/coregrind/pub_core_machine.h
branches/THUMB/include/pub_tool_machine.h
Modified: branches/THUMB/coregrind/m_coredump/coredump-elf.c
===================================================================
--- branches/THUMB/coregrind/m_coredump/coredump-elf.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_coredump/coredump-elf.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -340,7 +340,7 @@
regs->ARM_ip = arch->vex.guest_R12;
regs->ARM_sp = arch->vex.guest_R13;
regs->ARM_lr = arch->vex.guest_R14;
- regs->ARM_pc = VG_ENCIN_TO_IP(arch->vex.guest_R15T);
+ regs->ARM_pc = arch->vex.guest_R15T;
regs->ARM_cpsr = LibVEX_GuestARM_get_cpsr( &((ThreadArchState*)arch)->vex );
#else
Modified: branches/THUMB/coregrind/m_debugger.c
===================================================================
--- branches/THUMB/coregrind/m_debugger.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_debugger.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -224,7 +224,7 @@
uregs.ARM_ip = vex->guest_R12;
uregs.ARM_sp = vex->guest_R13;
uregs.ARM_lr = vex->guest_R14;
- uregs.ARM_pc = VG_ENCIN_TO_IP(vex->guest_R15T);
+ uregs.ARM_pc = vex->guest_R15T;
uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex);
return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs);
Modified: branches/THUMB/coregrind/m_debuginfo/debuginfo.c
===================================================================
--- branches/THUMB/coregrind/m_debuginfo/debuginfo.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_debuginfo/debuginfo.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -3057,7 +3057,7 @@
continue; /* ignore obviously stupid cases */
if (consider_vars_in_frame( dname1, dname2,
data_addr,
- VG_(get_ENCIP_IP)(tid),
+ VG_(get_IP)(tid),
VG_(get_SP)(tid),
VG_(get_FP)(tid), tid, 0 )) {
zterm_XA( dname1 );
Modified: branches/THUMB/coregrind/m_execontext.c
===================================================================
--- branches/THUMB/coregrind/m_execontext.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_execontext.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -311,7 +311,7 @@
if (first_ip_only) {
n_ips = 1;
- ips[0] = VG_(get_ENCIP_IP)(tid);
+ ips[0] = VG_(get_IP)(tid);
} else {
n_ips = VG_(get_StackTrace)( tid, ips, VG_(clo_backtrace_size),
NULL/*array to dump SP values in*/,
Modified: branches/THUMB/coregrind/m_machine.c
===================================================================
--- branches/THUMB/coregrind/m_machine.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_machine.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -39,41 +39,27 @@
#include "pub_core_debuglog.h"
-#define ENCIN_PTR(regs) ((regs).vex.VG_ENCIN_PTR)
+#define INSTR_PTR(regs) ((regs).vex.VG_INSTR_PTR)
#define STACK_PTR(regs) ((regs).vex.VG_STACK_PTR)
#define FRAME_PTR(regs) ((regs).vex.VG_FRAME_PTR)
-Addr VG_(get_ENCIP) ( ThreadId tid ) {
- return ENCIN_PTR( VG_(threads)[tid].arch );
+Addr VG_(get_IP) ( ThreadId tid ) {
+ return INSTR_PTR( VG_(threads)[tid].arch );
}
-Addr VG_(get_ENCIP_IP) ( ThreadId tid ) {
- return VG_ENCIN_TO_IP(ENCIN_PTR( VG_(threads)[tid].arch ));
-}
-UWord VG_(get_ENCIP_AUX) ( ThreadId tid ) {
- return VG_ENCIN_TO_AUX(ENCIN_PTR( VG_(threads)[tid].arch ));
-}
-
Addr VG_(get_SP) ( ThreadId tid ) {
return STACK_PTR( VG_(threads)[tid].arch );
}
-
Addr VG_(get_FP) ( ThreadId tid ) {
return FRAME_PTR( VG_(threads)[tid].arch );
}
-
-void VG_(set_ENCIP) ( ThreadId tid, Addr encip ) {
- ENCIN_PTR( VG_(threads)[tid].arch ) = encip;
+void VG_(set_IP) ( ThreadId tid, Addr ip ) {
+ INSTR_PTR( VG_(threads)[tid].arch ) = ip;
}
-void VG_(set_ENCIP_2) ( ThreadId tid, Addr ip, UWord aux ) {
- ENCIN_PTR( VG_(threads)[tid].arch ) = VG_IP_AUX_TO_ENCIN(ip, aux);
-}
-
void VG_(set_SP) ( ThreadId tid, Addr sp ) {
STACK_PTR( VG_(threads)[tid].arch ) = sp;
}
-
void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs,
ThreadId tid )
{
@@ -109,8 +95,6 @@
# else
# error "Unknown arch"
# endif
- /* Ensure the starting PC is properly decoded. */
- regs->r_pc = VG_ENCIN_TO_IP(regs->r_pc);
}
Modified: branches/THUMB/coregrind/m_main.c
===================================================================
--- branches/THUMB/coregrind/m_main.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_main.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -2523,8 +2523,7 @@
function entry point, not a fn descriptor, so can use it
directly. However, we need to set R2 (the toc pointer)
appropriately. */
- /* INTERWORKING FIXME: assumes wrapper runs in ARM mode */
- VG_(set_ENCIP_2)(tid, __libc_freeres_wrapper, 0);
+ VG_(set_IP)(tid, __libc_freeres_wrapper);
# if defined(VGP_ppc64_linux)
VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
# endif
Modified: branches/THUMB/coregrind/m_scheduler/scheduler.c
===================================================================
--- branches/THUMB/coregrind/m_scheduler/scheduler.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_scheduler/scheduler.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -654,7 +654,7 @@
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1));
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1));
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1));
-# endif
+# endif
# if defined(VGA_arm)
/* arm guest_state VFP regs must be 8 byte aligned for
@@ -823,7 +823,7 @@
retval = VG_TRC_FAULT_SIGNAL;
} else {
/* store away the guest program counter */
- VG_(set_ENCIP)( tid, argblock[2] );
+ VG_(set_IP)( tid, argblock[2] );
if (argblock[3] == argblock[1])
/* the guest state pointer afterwards was unchanged */
retval = VG_TRC_BORING;
@@ -847,16 +847,16 @@
static void handle_tt_miss ( ThreadId tid )
{
Bool found;
- Addr encip = VG_(get_ENCIP)(tid);
+ Addr ip = VG_(get_IP)(tid);
/* Trivial event. Miss in the fast-cache. Do a full
lookup for it. */
- found = VG_(search_transtab)( NULL, encip, True/*upd_fast_cache*/ );
+ found = VG_(search_transtab)( NULL, ip, True/*upd_fast_cache*/ );
if (UNLIKELY(!found)) {
/* Not found; we need to request a translation. */
- if (VG_(translate)( tid, encip, /*debug*/False, 0/*not verbose*/,
+ if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/,
bbs_done, True/*allow redirection*/ )) {
- found = VG_(search_transtab)( NULL, encip, True );
+ found = VG_(search_transtab)( NULL, ip, True );
vg_assert2(found, "VG_TRC_INNER_FASTMISS: missing tt_fast entry");
} else {
@@ -904,15 +904,17 @@
static UInt/*trc*/ handle_noredir_jump ( ThreadId tid )
{
AddrH hcode = 0;
- Addr encip = VG_(get_ENCIP)(tid);
+ Addr ip = VG_(get_IP)(tid);
- Bool found = VG_(search_unredir_transtab)( &hcode, encip );
+ Bool found = VG_(search_unredir_transtab)( &hcode, ip );
if (!found) {
/* Not found; we need to request a translation. */
- if (VG_(translate)( tid, encip, /*debug*/False, 0/*not verbose*/,
- bbs_done, False/*NO REDIRECTION*/ )) {
- found = VG_(search_unredir_transtab)( &hcode, encip );
+ if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/, bbs_done,
+ False/*NO REDIRECTION*/ )) {
+
+ found = VG_(search_unredir_transtab)( &hcode, ip );
vg_assert2(found, "unredir translation missing after creation?!");
+
} else {
// If VG_(translate)() fails, it's because it had to throw a
// signal because the client jumped to a bad address. That
@@ -1171,7 +1173,7 @@
case VEX_TRC_JMP_NODECODE:
VG_(umsg)(
"valgrind: Unrecognised instruction at address %#lx.\n",
- VG_(get_ENCIP_IP)(tid));
+ VG_(get_IP)(tid));
#define M(a) VG_(umsg)(a "\n");
M("Your program just tried to execute an instruction that Valgrind" );
M("did not recognise. There are two possible reasons for this." );
@@ -1184,8 +1186,7 @@
M("Either way, Valgrind will now raise a SIGILL signal which will" );
M("probably kill your program." );
#undef M
- // INTERWORKING FIXME is this correct (the use of get_ENCIP) ?
- VG_(synth_sigill)(tid, VG_(get_ENCIP)(tid));
+ VG_(synth_sigill)(tid, VG_(get_IP)(tid));
break;
case VEX_TRC_JMP_TINVAL:
Modified: branches/THUMB/coregrind/m_sigframe/sigframe-arm-linux.c
===================================================================
--- branches/THUMB/coregrind/m_sigframe/sigframe-arm-linux.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_sigframe/sigframe-arm-linux.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -139,7 +139,7 @@
SC2(ip,R12);
SC2(sp,R13);
SC2(lr,R14);
- SC2(pc,R15T); // INTERWORKING FIXME
+ SC2(pc,R15T);
// afaics, this is used for two purposes:
// * so the guest can see the faulting address. Hence it needs
// to be unencoded (the real insn IP)
@@ -241,21 +241,19 @@
tst->arch.vex.guest_R1 = (Addr)&rsf->info;
tst->arch.vex.guest_R2 = (Addr)&rsf->sig.uc;
}
- else{
+ else {
build_sigframe(tst, (struct sigframe *)sp, siginfo, siguc,
handler, flags, mask, restorer);
- }
+ }
VG_(set_SP)(tid, sp);
VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR,
sizeof(Addr));
- tst->arch.vex.guest_R0 = sigNo;
+ tst->arch.vex.guest_R0 = sigNo;
- if(flags & VKI_SA_RESTORER)
- tst->arch.vex.guest_R14 = (Addr) restorer;
+ if (flags & VKI_SA_RESTORER)
+ tst->arch.vex.guest_R14 = (Addr) restorer;
- // INTERWORKING FIXME this is almost certainly wrong. But how
- // do we know which insn set is to be used for the signal handler?
tst->arch.vex.guest_R15T = (Addr) handler; /* R15 == PC */
}
@@ -319,7 +317,7 @@
REST(ip,R12);
REST(sp,R13);
REST(lr,R14);
- REST(pc,R15T); // INTERWORKING FIXME see comments above
+ REST(pc,R15T);
# undef REST
tst->arch.vex_shadow1 = priv->vex_shadow1;
@@ -331,7 +329,7 @@
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
"vg_pop_signal_frame (thread %d): "
- "isRT=%d valid magic; PC(encoded)=%#x",
+ "isRT=%d valid magic; PC=%#x",
tid, has_siginfo, tst->arch.vex.guest_R15T);
/* tell the tools */
Modified: branches/THUMB/coregrind/m_signals.c
===================================================================
--- branches/THUMB/coregrind/m_signals.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_signals.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -2362,7 +2362,7 @@
if (VG_(clo_trace_signals)) {
VG_(dmsg)("sync signal handler: "
"signal=%d, si_code=%d, EIP=%#lx, eip=%#lx, from %s\n",
- sigNo, info->si_code, VG_(get_ENCIP_IP)(tid),
+ sigNo, info->si_code, VG_(get_IP)(tid),
VG_UCONTEXT_INSTR_PTR(uc),
( from_user ? "user" : "kernel" ));
}
Modified: branches/THUMB/coregrind/m_translate.c
===================================================================
--- branches/THUMB/coregrind/m_translate.c 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/m_translate.c 2010-08-22 10:29:32 UTC (rev 11275)
@@ -1253,7 +1253,6 @@
TID is the identity of the thread requesting this translation.
*/
-// INTERWORKING FIXME this requires careful consideration
Bool VG_(translate) ( ThreadId tid,
Addr64 nraddr,
Bool debugging_translation,
Modified: branches/THUMB/coregrind/pub_core_machine.h
===================================================================
--- branches/THUMB/coregrind/pub_core_machine.h 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/coregrind/pub_core_machine.h 2010-08-22 10:29:32 UTC (rev 11275)
@@ -96,12 +96,9 @@
# define VG_STACK_PTR guest_GPR1
# define VG_FRAME_PTR guest_GPR1 // No frame ptr for PPC
#elif defined(VGA_arm)
-# define VG_ENCIN_PTR guest_R15T
+# define VG_INSTR_PTR guest_R15T
# define VG_STACK_PTR guest_R13
# define VG_FRAME_PTR guest_R11
-# define VG_ENCIN_TO_IP(_encin) ((_encin) & ~1UL)
-# define VG_ENCIN_TO_AUX(_encin) ((_encin) & 1UL)
-# define VG_IP_AUX_TO_ENCIN(_ip,_aux) ((_ip) & ~1UL) | ((_aux) & 1UL)
#else
# error Unknown arch
#endif
@@ -113,18 +110,14 @@
//-------------------------------------------------------------
-// Guest state accessors not visible to tools (although they
-// could be, I guess)
-Addr VG_(get_ENCIP) ( ThreadId tid );
-Addr VG_(get_ENCIP_IP) ( ThreadId tid );
-UWord VG_(get_ENCIP_AUX) ( ThreadId tid );
+// Guest state accessors that are not visible to tools. The only
+// ones that are visible are get_IP and get_SP.
-Addr VG_(get_SP) ( ThreadId tid );
+//Addr VG_(get_IP) ( ThreadId tid ); // in pub_tool_machine.h
+//Addr VG_(get_SP) ( ThreadId tid ); // in pub_tool_machine.h
Addr VG_(get_FP) ( ThreadId tid );
-void VG_(set_ENCIP) ( ThreadId tid, Addr encip );
-void VG_(set_ENCIP_2) ( ThreadId tid, Addr ip, UWord aux );
-
+void VG_(set_IP) ( ThreadId tid, Addr encip );
void VG_(set_SP) ( ThreadId tid, Addr sp );
Modified: branches/THUMB/include/pub_tool_machine.h
===================================================================
--- branches/THUMB/include/pub_tool_machine.h 2010-08-21 11:47:01 UTC (rev 11274)
+++ branches/THUMB/include/pub_tool_machine.h 2010-08-22 10:29:32 UTC (rev 11275)
@@ -59,7 +59,7 @@
// Supplement 1.7
#elif defined(VGP_arm_linux)
-# define VG_MIN_INSTR_SZB 4
+# define VG_MIN_INSTR_SZB 2
# define VG_MAX_INSTR_SZB 4
# define VG_CLREQ_SZB 28
# define VG_STACK_REDZONE_SZB 0
@@ -99,8 +99,10 @@
#endif
// Guest state accessors
-// Currently all in the core_ header, until we know
-// they are needed here
+// Are mostly in the core_ header.
+// Only these two are available to tools.
+Addr VG_(get_IP) ( ThreadId tid );
+Addr VG_(get_SP) ( ThreadId tid );
// For get/set, 'area' is where the asked-for guest state will be copied
|