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From: <sv...@va...> - 2009-11-26 17:43:26
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Author: sewardj
Date: 2009-11-26 17:43:09 +0000 (Thu, 26 Nov 2009)
New Revision: 1931
Log:
Merge revs 1924:1929 from trunk (viz, resync to 1929).
Modified:
branches/ARM/priv/guest_amd64_helpers.c
branches/ARM/priv/host_amd64_defs.c
Modified: branches/ARM/priv/guest_amd64_helpers.c
===================================================================
--- branches/ARM/priv/guest_amd64_helpers.c 2009-11-26 17:17:37 UTC (rev 1930)
+++ branches/ARM/priv/guest_amd64_helpers.c 2009-11-26 17:43:09 UTC (rev 1931)
@@ -1014,6 +1014,16 @@
binop(Iop_Shl64,cc_dep1,mkU8(32))));
}
+ if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondS)) {
+ /* long sub/cmp, then S (negative) --> test (dst-src <s 0) */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpLT64S,
+ binop(Iop_Sub64,
+ binop(Iop_Shl64, cc_dep1, mkU8(32)),
+ binop(Iop_Shl64, cc_dep2, mkU8(32))),
+ mkU64(0)));
+ }
+
/*---------------- SUBW ----------------*/
if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondZ)) {
Modified: branches/ARM/priv/host_amd64_defs.c
===================================================================
--- branches/ARM/priv/host_amd64_defs.c 2009-11-26 17:17:37 UTC (rev 1930)
+++ branches/ARM/priv/host_amd64_defs.c 2009-11-26 17:43:09 UTC (rev 1931)
@@ -2335,10 +2335,26 @@
if (i->Ain.Alu64R.op == Aalu_MOV) {
switch (i->Ain.Alu64R.src->tag) {
case Armi_Imm:
- *p++ = toUChar(0x48 + (1 & iregBit3(i->Ain.Alu64R.dst)));
- *p++ = 0xC7;
- *p++ = toUChar(0xC0 + iregBits210(i->Ain.Alu64R.dst));
- p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
+ if (0 == (i->Ain.Alu64R.src->Armi.Imm.imm32 & ~0xFFF)) {
+ /* Actually we could use this form for constants in
+ the range 0 through 0x7FFFFFFF inclusive, but
+ limit it to a small range for verifiability
+ purposes. */
+ /* Generate "movl $imm32, 32-bit-register" and let
+ the default zero-extend rule cause the upper half
+ of the dst to be zeroed out too. This saves 1
+ and sometimes 2 bytes compared to the more
+ obvious encoding in the 'else' branch. */
+ if (1 & iregBit3(i->Ain.Alu64R.dst))
+ *p++ = 0x41;
+ *p++ = 0xB8 + iregBits210(i->Ain.Alu64R.dst);
+ p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
+ } else {
+ *p++ = toUChar(0x48 + (1 & iregBit3(i->Ain.Alu64R.dst)));
+ *p++ = 0xC7;
+ *p++ = toUChar(0xC0 + iregBits210(i->Ain.Alu64R.dst));
+ p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
+ }
goto done;
case Armi_Reg:
*p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
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