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From: <sv...@va...> - 2008-05-13 08:39:53
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Author: sewardj
Date: 2008-05-13 09:39:58 +0100 (Tue, 13 May 2008)
New Revision: 8056
Log:
Merge r7384 (tool&core-side support for SSSE3 insns)
Modified:
branches/VALGRIND_3_3_BRANCH/memcheck/mc_translate.c
Modified: branches/VALGRIND_3_3_BRANCH/memcheck/mc_translate.c
===================================================================
--- branches/VALGRIND_3_3_BRANCH/memcheck/mc_translate.c 2008-05-12 22:15:15 UTC (rev 8055)
+++ branches/VALGRIND_3_3_BRANCH/memcheck/mc_translate.c 2008-05-13 08:39:58 UTC (rev 8056)
@@ -1924,6 +1924,7 @@
case Iop_SarN32x2:
case Iop_ShlN16x4:
case Iop_ShlN32x2:
+ case Iop_ShlN8x8:
/* Same scheme as with all other shifts. */
complainIfUndefined(mce, atom2);
return assignNew(mce, Ity_I64, binop(op, vatom1, atom2));
@@ -1963,6 +1964,7 @@
return binary16Ix4(mce, vatom1, vatom2);
case Iop_Sub32x2:
+ case Iop_Mul32x2:
case Iop_CmpGT32Sx2:
case Iop_CmpEQ32x2:
case Iop_Add32x2:
@@ -1975,8 +1977,20 @@
case Iop_InterleaveHI32x2:
case Iop_InterleaveHI16x4:
case Iop_InterleaveHI8x8:
+ case Iop_CatOddLanes16x4:
+ case Iop_CatEvenLanes16x4:
return assignNew(mce, Ity_I64, binop(op, vatom1, vatom2));
+ /* Perm8x8: rearrange values in left arg using steering values
+ from right arg. So rearrange the vbits in the same way but
+ pessimise wrt steering values. */
+ case Iop_Perm8x8:
+ return mkUifU64(
+ mce,
+ assignNew(mce, Ity_I64, binop(op, vatom1, atom2)),
+ mkPCast8x8(mce, vatom2)
+ );
+
/* V128-bit SIMD */
case Iop_ShrN16x8:
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