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From: <sv...@va...> - 2007-05-08 18:00:26
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Author: sewardj
Date: 2007-05-08 19:00:19 +0100 (Tue, 08 May 2007)
New Revision: 1770
Log:
Get rid of Iop_Neg64/32/16/8 as they are no longer used by Memcheck,
and any uses as generated by the front ends are so infrequent that
generating the equivalent Sub(0, ..) is good enough. This gets rid of
quite a few lines of code. Add isel cases for Sub(0, ..) patterns so
that the x86/amd64 backends still generate negl/negq where possible.
Modified:
branches/CGTUNE/priv/guest-ppc/toIR.c
branches/CGTUNE/priv/guest-x86/toIR.c
branches/CGTUNE/priv/host-amd64/isel.c
branches/CGTUNE/priv/host-ppc/isel.c
branches/CGTUNE/priv/host-x86/isel.c
branches/CGTUNE/priv/ir/irdefs.c
branches/CGTUNE/priv/ir/iropt.c
branches/CGTUNE/pub/libvex_ir.h
Modified: branches/CGTUNE/priv/guest-ppc/toIR.c
===================================================================
--- branches/CGTUNE/priv/guest-ppc/toIR.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/guest-ppc/toIR.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -783,7 +783,7 @@
op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 ||
op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 ||
op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 ||
- op8 == Iop_Not8 || op8 == Iop_Neg8 );
+ op8 == Iop_Not8 );
adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : (ty==Ity_I32 ? 2 : 3));
return adj + op8;
}
Modified: branches/CGTUNE/priv/guest-x86/toIR.c
===================================================================
--- branches/CGTUNE/priv/guest-x86/toIR.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/guest-x86/toIR.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -684,7 +684,7 @@
|| op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8
|| op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8
|| op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8
- || op8 == Iop_Not8 || op8 == Iop_Neg8);
+ || op8 == Iop_Not8);
adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2);
return adj + op8;
}
@@ -2631,7 +2631,7 @@
dst1 = newTemp(ty);
assign(dst0, mkU(ty,0));
assign(src, getIReg(sz,eregOfRM(modrm)));
- assign(dst1, unop(mkSizedOp(ty,Iop_Neg8), mkexpr(src)));
+ assign(dst1, binop(mkSizedOp(ty,Iop_Sub8), mkexpr(dst0), mkexpr(src)));
setFlags_DEP1_DEP2(Iop_Sub8, dst0, src, ty);
putIReg(sz, eregOfRM(modrm), mkexpr(dst1));
DIP("neg%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
@@ -2693,7 +2693,7 @@
dst1 = newTemp(ty);
assign(dst0, mkU(ty,0));
assign(src, mkexpr(t1));
- assign(dst1, unop(mkSizedOp(ty,Iop_Neg8), mkexpr(src)));
+ assign(dst1, binop(mkSizedOp(ty,Iop_Sub8), mkexpr(dst0), mkexpr(src)));
setFlags_DEP1_DEP2(Iop_Sub8, dst0, src, ty);
storeLE( mkexpr(addr), mkexpr(dst1) );
DIP("neg%c %s\n", nameISize(sz), dis_buf);
Modified: branches/CGTUNE/priv/host-amd64/isel.c
===================================================================
--- branches/CGTUNE/priv/host-amd64/isel.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/host-amd64/isel.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -278,15 +278,22 @@
return toBool(x == y1);
}
-//.. /* Is this a 32-bit zero expression? */
-//..
-//.. static Bool isZero32 ( IRExpr* e )
-//.. {
-//.. return e->tag == Iex_Const
-//.. && e->Iex.Const.con->tag == Ico_U32
-//.. && e->Iex.Const.con->Ico.U32 == 0;
-//.. }
+/* Is this a 64-bit zero expression? */
+static Bool isZeroU64 ( IRExpr* e )
+{
+ return e->tag == Iex_Const
+ && e->Iex.Const.con->tag == Ico_U64
+ && e->Iex.Const.con->Ico.U64 == 0ULL;
+}
+
+static Bool isZeroU32 ( IRExpr* e )
+{
+ return e->tag == Iex_Const
+ && e->Iex.Const.con->tag == Ico_U32
+ && e->Iex.Const.con->Ico.U32 == 0;
+}
+
/* Make a int reg-reg move. */
static AMD64Instr* mk_iMOVsd_RR ( HReg src, HReg dst )
@@ -841,16 +848,17 @@
AMD64AluOp aluOp;
AMD64ShiftOp shOp;
-//..
-//.. /* Pattern: Sub32(0,x) */
-//.. if (e->Iex.Binop.op == Iop_Sub32 && isZero32(e->Iex.Binop.arg1)) {
-//.. HReg dst = newVRegI(env);
-//.. HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. addInstr(env, mk_iMOVsd_RR(reg,dst));
-//.. addInstr(env, X86Instr_Unary32(Xun_NEG,X86RM_Reg(dst)));
-//.. return dst;
-//.. }
-//..
+ /* Pattern: Sub64(0,x) */
+ /* and: Sub32(0,x) */
+ if ((e->Iex.Binop.op == Iop_Sub64 && isZeroU64(e->Iex.Binop.arg1))
+ || (e->Iex.Binop.op == Iop_Sub32 && isZeroU32(e->Iex.Binop.arg1))) {
+ HReg dst = newVRegI(env);
+ HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, mk_iMOVsd_RR(reg,dst));
+ addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
+ return dst;
+ }
+
/* Is it an addition or logical style op? */
switch (e->Iex.Binop.op) {
case Iop_Add8: case Iop_Add16: case Iop_Add32: case Iop_Add64:
@@ -1449,16 +1457,6 @@
AMD64RMI_Reg(tmp), dst));
return dst;
}
- case Iop_Neg8:
- case Iop_Neg16:
- case Iop_Neg32:
- case Iop_Neg64: {
- HReg dst = newVRegI(env);
- HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, mk_iMOVsd_RR(reg,dst));
- addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
- return dst;
- }
case Iop_CmpwNEZ64: {
HReg dst = newVRegI(env);
Modified: branches/CGTUNE/priv/host-ppc/isel.c
===================================================================
--- branches/CGTUNE/priv/host-ppc/isel.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/host-ppc/isel.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -1705,17 +1705,6 @@
addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
return r_dst;
}
- case Iop_Neg8:
- case Iop_Neg16:
- case Iop_Neg32:
- case Iop_Neg64: {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
- if (op_unop == Iop_Neg64 && !mode64)
- goto irreducible;
- addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src));
- return r_dst;
- }
case Iop_Left8:
case Iop_Left32:
@@ -1805,8 +1794,6 @@
case Iop_32to16:
case Iop_64to8:
/* These are no-ops. */
- if (op_unop == Iop_Neg64 && !mode64)
- goto irreducible;
return iselWordExpr_R(env, e->Iex.Unop.arg);
/* ReinterpF64asI64(e) */
@@ -2816,22 +2803,6 @@
*rLo = tLo;
return;
}
-
- case Iop_Neg64: {
- HReg yLo, yHi;
- HReg zero = newVRegI(env);
- HReg tLo = newVRegI(env);
- HReg tHi = newVRegI(env);
- iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_LI(zero, 0, False/*mode32*/));
- addInstr(env, PPCInstr_AddSubC( False/*sub*/, True/*set carry*/,
- tLo, zero, yLo));
- addInstr(env, PPCInstr_AddSubC( False/*sub*/, False/*read carry*/,
- tHi, zero, yHi));
- *rHi = tHi;
- *rLo = tLo;
- return;
- }
/* ReinterpF64asI64(e) */
/* Given an IEEE754 double, produce an I64 with the same bit
Modified: branches/CGTUNE/priv/host-x86/isel.c
===================================================================
--- branches/CGTUNE/priv/host-x86/isel.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/host-x86/isel.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -120,6 +120,13 @@
&& e->Iex.Const.con->Ico.U8 == 0;
}
+static Bool isZeroU32 ( IRExpr* e )
+{
+ return e->tag == Iex_Const
+ && e->Iex.Const.con->tag == Ico_U32
+ && e->Iex.Const.con->Ico.U32 == 0;
+}
+
static Bool isZeroU64 ( IRExpr* e )
{
return e->tag == Iex_Const
@@ -805,6 +812,15 @@
X86AluOp aluOp;
X86ShiftOp shOp;
+ /* Pattern: Sub32(0,x) */
+ if (e->Iex.Binop.op == Iop_Sub32 && isZeroU32(e->Iex.Binop.arg1)) {
+ HReg dst = newVRegI(env);
+ HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, mk_iMOVsd_RR(reg,dst));
+ addInstr(env, X86Instr_Unary32(Xun_NEG,dst));
+ return dst;
+ }
+
/* Is it an addition or logical style op? */
switch (e->Iex.Binop.op) {
case Iop_Add8: case Iop_Add16: case Iop_Add32:
@@ -1194,15 +1210,6 @@
X86RMI_Reg(tmp), dst));
return dst;
}
- case Iop_Neg8:
- case Iop_Neg16:
- case Iop_Neg32: {
- HReg dst = newVRegI(env);
- HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, mk_iMOVsd_RR(reg,dst));
- addInstr(env, X86Instr_Unary32(Xun_NEG,dst));
- return dst;
- }
case Iop_CmpwNEZ32: {
HReg dst = newVRegI(env);
@@ -2494,24 +2501,6 @@
return;
}
- /* Neg64(e) */
- case Iop_Neg64: {
- HReg yLo, yHi;
- HReg tLo = newVRegI(env);
- HReg tHi = newVRegI(env);
- /* yHi:yLo = arg */
- iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
- /* tLo = 0 - yLo, and set carry */
- addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tLo));
- addInstr(env, X86Instr_Alu32R(Xalu_SUB, X86RMI_Reg(yLo), tLo));
- /* tHi = 0 - yHi - carry */
- addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tHi));
- addInstr(env, X86Instr_Alu32R(Xalu_SBB, X86RMI_Reg(yHi), tHi));
- *rHi = tHi;
- *rLo = tLo;
- return;
- }
-
/* --- patterns rooted at: CmpwNEZ64 --- */
/* CmpwNEZ64(e) */
Modified: branches/CGTUNE/priv/ir/irdefs.c
===================================================================
--- branches/CGTUNE/priv/ir/irdefs.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/ir/irdefs.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -217,11 +217,6 @@
case Iop_CmpORD64U: vex_printf("CmpORD64U"); return;
case Iop_CmpORD64S: vex_printf("CmpORD64S"); return;
- case Iop_Neg8: vex_printf("Neg8"); return;
- case Iop_Neg16: vex_printf("Neg16"); return;
- case Iop_Neg32: vex_printf("Neg32"); return;
- case Iop_Neg64: vex_printf("Neg64"); return;
-
case Iop_DivU32: vex_printf("DivU32"); return;
case Iop_DivS32: vex_printf("DivS32"); return;
case Iop_DivU64: vex_printf("DivU64"); return;
@@ -1525,14 +1520,13 @@
case Iop_Shl64: case Iop_Shr64: case Iop_Sar64:
BINARY(Ity_I64,Ity_I8, Ity_I64);
- case Iop_Not8: case Iop_Neg8:
+ case Iop_Not8:
UNARY(Ity_I8, Ity_I8);
- case Iop_Not16: case Iop_Neg16:
+ case Iop_Not16:
UNARY(Ity_I16, Ity_I16);
- case Iop_Not32: case Iop_Neg32:
+ case Iop_Not32:
UNARY(Ity_I32, Ity_I32);
- case Iop_Neg64:
case Iop_Not64:
case Iop_CmpNEZ32x2: case Iop_CmpNEZ16x4: case Iop_CmpNEZ8x8:
UNARY(Ity_I64, Ity_I64);
Modified: branches/CGTUNE/priv/ir/iropt.c
===================================================================
--- branches/CGTUNE/priv/ir/iropt.c 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/priv/ir/iropt.c 2007-05-08 18:00:19 UTC (rev 1770)
@@ -1011,19 +1011,6 @@
notBool(e->Iex.Unop.arg->Iex.Const.con->Ico.U1)));
break;
- case Iop_Neg64:
- e2 = IRExpr_Const(IRConst_U64(
- - (e->Iex.Unop.arg->Iex.Const.con->Ico.U64)));
- break;
- case Iop_Neg32:
- e2 = IRExpr_Const(IRConst_U32(
- - (e->Iex.Unop.arg->Iex.Const.con->Ico.U32)));
- break;
- case Iop_Neg8:
- e2 = IRExpr_Const(IRConst_U8(toUChar(
- - (e->Iex.Unop.arg->Iex.Const.con->Ico.U8))));
- break;
-
case Iop_64to8: {
ULong w64 = e->Iex.Unop.arg->Iex.Const.con->Ico.U64;
w64 &= 0xFFULL;
Modified: branches/CGTUNE/pub/libvex_ir.h
===================================================================
--- branches/CGTUNE/pub/libvex_ir.h 2007-05-08 13:45:27 UTC (rev 1769)
+++ branches/CGTUNE/pub/libvex_ir.h 2007-05-08 18:00:19 UTC (rev 1770)
@@ -422,7 +422,6 @@
Iop_CmpNE8, Iop_CmpNE16, Iop_CmpNE32, Iop_CmpNE64,
/* Tags for unary ops */
Iop_Not8, Iop_Not16, Iop_Not32, Iop_Not64,
- Iop_Neg8, Iop_Neg16, Iop_Neg32, Iop_Neg64,
/* -- Ordering not important after here. -- */
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