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From: <sv...@va...> - 2007-01-09 15:20:18
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Author: sewardj
Date: 2007-01-09 15:20:07 +0000 (Tue, 09 Jan 2007)
New Revision: 1721
Log:
Add 'missing' primop Iop_ReinterpF32asI32 and code generation support
for it on x86 hosts.
Modified:
trunk/priv/host-x86/isel.c
trunk/priv/ir/irdefs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2007-01-08 06:02:53 UTC (rev 1720)
+++ trunk/priv/host-x86/isel.c 2007-01-09 15:20:07 UTC (rev 1721)
@@ -1143,6 +1143,29 @@
return dst;
}
=20
+ /* ReinterpF32asI32(e) */
+ /* Given an IEEE754 single, produce an I32 with the same bit
+ pattern. Keep stack 8-aligned even though only using 4
+ bytes. */
+ case Iop_ReinterpF32asI32: {
+ HReg rf =3D iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst =3D newVRegI(env);
+ X86AMode* zero_esp =3D X86AMode_IR(0, hregX86_ESP());
+ /* paranoia */
+ set_FPU_rounding_default(env);
+ /* subl $8, %esp */
+ sub_from_esp(env, 8);
+ /* gstF %rf, 0(%esp) */
+ addInstr(env,
+ X86Instr_FpLdSt(False/*store*/, 4, rf, zero_esp));
+ /* movl 0(%esp), %dst */
+ addInstr(env,=20
+ X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(zero_esp), dst=
));
+ /* addl $8, %esp */
+ add_to_esp(env, 8);
+ return dst;
+ }
+
case Iop_16to8:
case Iop_32to8:
case Iop_32to16:
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2007-01-08 06:02:53 UTC (rev 1720)
+++ trunk/priv/ir/irdefs.c 2007-01-09 15:20:07 UTC (rev 1721)
@@ -294,6 +294,7 @@
=20
case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return;
case Iop_ReinterpI64asF64: vex_printf("ReinterpI64asF64"); return;
+ case Iop_ReinterpF32asI32: vex_printf("ReinterpF32asI32"); return;
case Iop_ReinterpI32asF32: vex_printf("ReinterpI32asF32"); return;
=20
case Iop_I32UtoFx4: vex_printf("Iop_I32UtoFx4"); return;
@@ -1655,6 +1656,7 @@
case Iop_ReinterpI64asF64: UNARY(Ity_I64, Ity_F64);
case Iop_ReinterpF64asI64: UNARY(Ity_F64, Ity_I64);
case Iop_ReinterpI32asF32: UNARY(Ity_I32, Ity_F32);
+ case Iop_ReinterpF32asI32: UNARY(Ity_F32, Ity_I32);
=20
case Iop_AtanF64: case Iop_Yl2xF64: case Iop_Yl2xp1F64:=20
case Iop_ScaleF64: case Iop_PRemF64: case Iop_PRem1F64:
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2007-01-08 06:02:53 UTC (rev 1720)
+++ trunk/pub/libvex_ir.h 2007-01-09 15:20:07 UTC (rev 1721)
@@ -590,7 +590,7 @@
/* Reinterpretation. Take an F64 and produce an I64 with=20
the same bit pattern, or vice versa. */
Iop_ReinterpF64asI64, Iop_ReinterpI64asF64,
- Iop_ReinterpI32asF32,
+ Iop_ReinterpF32asI32, Iop_ReinterpI32asF32,
=20
/* --- guest x86/amd64 specifics, not mandated by 754. --- */
=20
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