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From: <sv...@va...> - 2006-12-27 21:38:41
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Author: sewardj
Date: 2006-12-27 21:38:35 +0000 (Wed, 27 Dec 2006)
New Revision: 1708
Log:
Merge r1707 (Enable lvxl and stvxl.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-27 21:21:14 UTC=
(rev 1707)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-27 21:38:35 UTC=
(rev 1708)
@@ -6862,10 +6862,9 @@
break;
=20
case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
- // XXX: lvxl gives explicit control over cache block replacement
DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
+ break;
=20
default:
vex_printf("dis_av_load(ppc)(opc2)\n");
@@ -6950,12 +6949,9 @@
break;
=20
case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
- // XXX: stvxl can give explicit control over cache block replacemen=
t
DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-// STORE(vS, 16, addr_align( mkexpr(EA), 16 ));
-// break;
+ storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+ break;
=20
default:
vex_printf("dis_av_store(ppc)(opc2)\n");
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