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From: <sv...@va...> - 2006-11-22 21:00:55
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Author: weidendo
Date: 2006-11-22 21:00:53 +0000 (Wed, 22 Nov 2006)
New Revision: 6367
Log:
Fix same cache simulation bug in callgrind as fixed
in r6365 for cachegrind.
This needs 3 fixes (the 4th is ifdef'd out) for the
3 versions of the simulator in callgrind.
Modified:
trunk/callgrind/sim.c
Modified: trunk/callgrind/sim.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/callgrind/sim.c 2006-11-22 11:41:07 UTC (rev 6366)
+++ trunk/callgrind/sim.c 2006-11-22 21:00:53 UTC (rev 6367)
@@ -300,10 +300,11 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) =3D=3D set2) {
+ UWord tag2 =3D (a+size-1) >> c->tag_shift;
=20
/* the call updates cache structures as side effect */
CacheResult res1 =3D cachesim_setref(c, set1, tag);
- CacheResult res2 =3D cachesim_setref(c, set2, tag);
+ CacheResult res2 =3D cachesim_setref(c, set2, tag2);
return ((res1 =3D=3D Miss) || (res2 =3D=3D Miss)) ? Miss : Hit;
=20
} else {
@@ -404,10 +405,11 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) =3D=3D set2) {
+ UWord tag2 =3D (a+size-1) >> c->tag_shift;
=20
/* the call updates cache structures as side effect */
CacheResult res1 =3D cachesim_setref_wb(c, ref, set1, tag);
- CacheResult res2 =3D cachesim_setref_wb(c, ref, set2, tag);
+ CacheResult res2 =3D cachesim_setref_wb(c, ref, set2, tag2);
=20
if ((res1 =3D=3D MissDirty) || (res2 =3D=3D MissDirty)) return MissDirt=
y;
return ((res1 =3D=3D Miss) || (res2 =3D=3D Miss)) ? Miss : Hit;
@@ -758,10 +760,11 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) =3D=3D set2) {
+ UWord tag2 =3D a >> c->tag_shift;
=20
/* the call updates cache structures as side effect */
CacheResult res1 =3D cacheuse_isMiss(c, set1, tag);
- CacheResult res2 =3D cacheuse_isMiss(c, set2, tag);
+ CacheResult res2 =3D cacheuse_isMiss(c, set2, tag2);
return ((res1 =3D=3D Miss) || (res2 =3D=3D Miss)) ? Miss : Hit;
=20
} else {
@@ -778,9 +781,10 @@
=
\
static CacheModelResult cacheuse##_##L##_doRead(Addr a, UChar size) =
\
{ =
\
- register UInt set1 =3D ( a >> L.line_size_bits) & (L.sets_min=
_1); \
- register UInt set2 =3D ((a+size-1) >> L.line_size_bits) & (L.sets_min=
_1); \
- register UWord tag =3D a & L.tag_mask; =
\
+ UInt set1 =3D ( a >> L.line_size_bits) & (L.sets_min_1); =
\
+ UInt set2 =3D ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); =
\
+ UWord tag =3D a & L.tag_mask; =
\
+ UWord tag2; =
\
int i, j, idx; =
\
UWord *set, tmp_tag; \
UInt use_mask; \
@@ -879,7 +883,8 @@
block2: =
\
set =3D &(L.tags[set2 << L.assoc_bits]); =
\
use_mask =3D L.line_end_mask[(a+size-1) & L.line_size_mask]; =
\
- if (tag =3D=3D (set[0] & L.tag_mask)) { =
\
+ tag2 =3D (a+size-1) & L.tag_mask; =
\
+ if (tag2 =3D=3D (set[0] & L.tag_mask)) { =
\
idx =3D (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); =
\
L.use[idx].count ++; =
\
L.use[idx].mask |=3D use_mask; =
\
@@ -889,7 +894,7 @@
return miss1; =
\
} =
\
for (i =3D 1; i < L.assoc; i++) { =
\
- if (tag =3D=3D (set[i] & L.tag_mask)) { \
+ if (tag2 =3D=3D (set[i] & L.tag_mask)) { \
tmp_tag =3D set[i]; =
\
for (j =3D i; j > 0; j--) { =
\
set[j] =3D set[j - 1]; =
\
@@ -908,7 +913,7 @@
for (j =3D L.assoc - 1; j > 0; j--) { =
\
set[j] =3D set[j - 1]; =
\
} =
\
- set[0] =3D tag | tmp_tag; =
\
+ set[0] =3D tag2 | tmp_tag; =
\
idx =3D (set2 << L.assoc_bits) | tmp_tag; =
\
miss2 =3D update_##L##_use(&L, idx, \
use_mask, (a+size-1) &~ L.line_size_mask); \
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