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From: <sv...@va...> - 2006-10-04 17:46:16
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Author: sewardj
Date: 2006-10-04 18:46:11 +0100 (Wed, 04 Oct 2006)
New Revision: 1667
Log:
Reinstate support for 'mcrfs'.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-09-30 00:30:46 UTC (rev 1666)
+++ trunk/priv/guest-ppc/toIR.c 2006-10-04 17:46:11 UTC (rev 1667)
@@ -6497,23 +6497,27 @@
break;
}
=20
-//zz case 0x040: { // mcrfs (Move to Condition Register from FPSCR, P=
PC32 p465)
-//zz UChar crfD =3D toUChar( IFIELD( theInstr, 23, 3 ) );
-//zz UChar b21to22 =3D toUChar( IFIELD( theInstr, 21, 2 ) );
-//zz UChar crfS =3D toUChar( IFIELD( theInstr, 18, 3 ) );
-//zz UChar b11to17 =3D toUChar( IFIELD( theInstr, 11, 7 ) );
-//zz=20
-//zz IRTemp tmp =3D newTemp(Ity_I32);
-//zz=20
-//zz if (b21to22 !=3D 0 || b11to17 !=3D 0 || flag_rC !=3D 0) {
-//zz vex_printf("dis_fp_scr(ppc)(instr,mcrfs)\n");
-//zz return False;
-//zz }
-//zz DIP("mcrfs crf%d,crf%d\n", crfD, crfS);
-//zz assign( tmp, getGST_field( PPC_GST_FPSCR, crfS ) );
-//zz putGST_field( PPC_GST_CR, mkexpr(tmp), crfD );
-//zz break;
-//zz }
+ case 0x040: { // mcrfs (Move to Condition Register from FPSCR, PPC32 =
p465)
+ UChar crfD =3D toUChar( IFIELD( theInstr, 23, 3 ) );
+ UChar b21to22 =3D toUChar( IFIELD( theInstr, 21, 2 ) );
+ UChar crfS =3D toUChar( IFIELD( theInstr, 18, 3 ) );
+ UChar b11to17 =3D toUChar( IFIELD( theInstr, 11, 7 ) );
+ IRTemp tmp =3D newTemp(Ity_I32);
+ IRExpr* fpscr_all;
+ if (b21to22 !=3D 0 || b11to17 !=3D 0 || flag_rC !=3D 0) {
+ vex_printf("dis_fp_scr(ppc)(instr,mcrfs)\n");
+ return False;
+ }
+ DIP("mcrfs crf%d,crf%d\n", crfD, crfS);
+ vassert(crfD < 8);
+ vassert(crfS < 8);
+ fpscr_all =3D getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN );
+ assign( tmp, binop(Iop_And32,
+ binop(Iop_Shr32,fpscr_all,mkU8(4 * (7-crfS))),
+ mkU32(0xF)) );
+ putGST_field( PPC_GST_CR, mkexpr(tmp), crfD );
+ break;
+ }
=20
case 0x046: { // mtfsb0 (Move to FPSCR Bit 0, PPC32 p478)
// Bit crbD of the FPSCR is cleared.
@@ -6545,8 +6549,9 @@
}
=20
case 0x247: { // mffs (Move from FPSCR, PPC32 p468)
- UChar frD_addr =3D ifieldRegDS(theInstr);
- UInt b11to20 =3D IFIELD(theInstr, 11, 10);
+ UChar frD_addr =3D ifieldRegDS(theInstr);
+ UInt b11to20 =3D IFIELD(theInstr, 11, 10);
+ IRExpr* fpscr_all =3D getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN =
);
=20
if (b11to20 !=3D 0) {
vex_printf("dis_fp_scr(ppc)(instr,mffs)\n");
@@ -6555,8 +6560,7 @@
DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
putFReg( frD_addr,
unop( Iop_ReinterpI64asF64,
- unop( Iop_32Uto64,=20
- getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ) )));
+ unop( Iop_32Uto64, fpscr_all )));
break;
}
=20
@@ -9004,7 +9008,7 @@
=20
/* Floating Point Status/Control Register Instructions */ =20
case 0x026: // mtfsb1
- /* case 0x040: // mcrfs */
+ case 0x040: // mcrfs
case 0x046: // mtfsb0
case 0x086: // mtfsfi
case 0x247: // mffs
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