|
From: <sv...@va...> - 2006-09-30 00:30:51
|
Author: sewardj
Date: 2006-09-30 01:30:46 +0100 (Sat, 30 Sep 2006)
New Revision: 1666
Log:
Fix up some function prototype confusion so it compiles again.
Modified:
branches/AIX5/priv/guest-amd64/gdefs.h
branches/AIX5/priv/guest-amd64/toIR.c
branches/AIX5/priv/guest-generic/bb_to_IR.c
branches/AIX5/priv/guest-generic/bb_to_IR.h
branches/AIX5/priv/guest-ppc/toIR.c
branches/AIX5/priv/guest-x86/gdefs.h
branches/AIX5/priv/guest-x86/toIR.c
branches/AIX5/priv/host-amd64/hdefs.h
branches/AIX5/priv/host-amd64/isel.c
branches/AIX5/priv/host-ppc/hdefs.c
branches/AIX5/priv/host-ppc/hdefs.h
branches/AIX5/priv/host-ppc/isel.c
branches/AIX5/priv/host-x86/hdefs.h
branches/AIX5/priv/host-x86/isel.c
branches/AIX5/priv/main/vex_main.c
Modified: branches/AIX5/priv/guest-amd64/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-amd64/gdefs.h 2006-09-29 22:26:57 UTC (rev 1=
665)
+++ branches/AIX5/priv/guest-amd64/gdefs.h 2006-09-30 00:30:46 UTC (rev 1=
666)
@@ -64,6 +64,7 @@
UChar* guest_code,
Long delta,
Addr64 guest_IP,
+ VexArch guest_arch,
VexArchInfo* archinfo,
VexMiscInfo* miscinfo,
Bool host_bigendian );
Modified: branches/AIX5/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-amd64/toIR.c 2006-09-29 22:26:57 UTC (rev 16=
65)
+++ branches/AIX5/priv/guest-amd64/toIR.c 2006-09-30 00:30:46 UTC (rev 16=
66)
@@ -14350,6 +14350,7 @@
UChar* guest_code_IN,
Long delta,
Addr64 guest_IP,
+ VexArch guest_arch,
VexArchInfo* archinfo,
VexMiscInfo* miscinfo,
Bool host_bigendian_IN )
Modified: branches/AIX5/priv/guest-generic/bb_to_IR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-generic/bb_to_IR.c 2006-09-29 22:26:57 UTC (=
rev 1665)
+++ branches/AIX5/priv/guest-generic/bb_to_IR.c 2006-09-30 00:30:46 UTC (=
rev 1666)
@@ -99,6 +99,7 @@
/*IN*/ Addr64 guest_IP_bbstart,
/*IN*/ Bool (*chase_into_ok)(void*,Addr64),
/*IN*/ Bool host_bigendian,
+ /*IN*/ VexArch arch_guest,
/*IN*/ VexArchInfo* archinfo_guest,
/*IN*/ VexMiscInfo* miscinfo_both,
/*IN*/ IRType guest_word_type,
@@ -232,6 +233,7 @@
guest_code,
delta,
guest_IP_curr_instr,
+ arch_guest,
archinfo_guest,
miscinfo_both,
host_bigendian );
Modified: branches/AIX5/priv/guest-generic/bb_to_IR.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-generic/bb_to_IR.h 2006-09-29 22:26:57 UTC (=
rev 1665)
+++ branches/AIX5/priv/guest-generic/bb_to_IR.h 2006-09-30 00:30:46 UTC (=
rev 1666)
@@ -140,6 +140,7 @@
/*IN*/ Addr64 guest_IP,
=20
/* Info about the guest architecture */
+ /*IN*/ VexArch guest_arch,
/*IN*/ VexArchInfo* archinfo,
=20
/* Misc info about guest and host */
@@ -164,6 +165,7 @@
/*IN*/ Addr64 guest_IP_bbstart,
/*IN*/ Bool (*chase_into_ok)(void*,Addr64),
/*IN*/ Bool host_bigendian,
+ /*IN*/ VexArch arch_guest,
/*IN*/ VexArchInfo* archinfo_guest,
/*IN*/ VexMiscInfo* miscinfo_both,
/*IN*/ IRType guest_word_type,
Modified: branches/AIX5/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-ppc/toIR.c 2006-09-29 22:26:57 UTC (rev 1665=
)
+++ branches/AIX5/priv/guest-ppc/toIR.c 2006-09-30 00:30:46 UTC (rev 1666=
)
@@ -9508,6 +9508,7 @@
UChar* guest_code_IN,
Long delta,
Addr64 guest_IP,
+ VexArch guest_arch,
VexArchInfo* archinfo,
VexMiscInfo* miscinfo,
Bool host_bigendian_IN )
Modified: branches/AIX5/priv/guest-x86/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-x86/gdefs.h 2006-09-29 22:26:57 UTC (rev 166=
5)
+++ branches/AIX5/priv/guest-x86/gdefs.h 2006-09-30 00:30:46 UTC (rev 166=
6)
@@ -64,6 +64,7 @@
UChar* guest_code,
Long delta,
Addr64 guest_IP,
+ VexArch guest_arch,
VexArchInfo* archinfo,
VexMiscInfo* miscinfo,
Bool host_bigendian );
Modified: branches/AIX5/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/guest-x86/toIR.c 2006-09-29 22:26:57 UTC (rev 1665=
)
+++ branches/AIX5/priv/guest-x86/toIR.c 2006-09-30 00:30:46 UTC (rev 1666=
)
@@ -12900,6 +12900,7 @@
UChar* guest_code_IN,
Long delta,
Addr64 guest_IP,
+ VexArch guest_arch,
VexArchInfo* archinfo,
VexMiscInfo* miscinfo,
Bool host_bigendian_IN )
Modified: branches/AIX5/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-amd64/hdefs.h 2006-09-29 22:26:57 UTC (rev 16=
65)
+++ branches/AIX5/priv/host-amd64/hdefs.h 2006-09-30 00:30:46 UTC (rev 16=
66)
@@ -725,7 +725,8 @@
extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool=
);
extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool=
);
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
-extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArchInfo*,
+extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArch,
+ VexArchInfo*,
VexMiscInfo* );
=20
#endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */
Modified: branches/AIX5/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-amd64/isel.c 2006-09-29 22:26:57 UTC (rev 166=
5)
+++ branches/AIX5/priv/host-amd64/isel.c 2006-09-30 00:30:46 UTC (rev 166=
6)
@@ -3801,7 +3801,8 @@
=20
/* Translate an entire BB to amd64 code. */
=20
-HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArchInfo* archinfo_host,
+HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArch arch_host,
+ VexArchInfo* archinfo_host,
VexMiscInfo* vmi/*UNUSED*/ )
{
Int i, j;
Modified: branches/AIX5/priv/host-ppc/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-ppc/hdefs.c 2006-09-29 22:26:57 UTC (rev 1665=
)
+++ branches/AIX5/priv/host-ppc/hdefs.c 2006-09-30 00:30:46 UTC (rev 1666=
)
@@ -1123,8 +1123,6 @@
=20
/* Pretty Print instructions */
static void ppLoadImm ( HReg dst, ULong imm, Bool mode64 ) {
-XXX tidy this up
-#if 1
vex_printf("li_word ");
ppHRegPPC(dst);
if (!mode64) {
@@ -1132,58 +1130,6 @@
} else {
vex_printf(",0x%016llx", imm);
}
-#else
- if (imm >=3D 0xFFFFFFFFFFFF8000ULL || imm < 0x8000) {
- // sign-extendable from 16 bits
- vex_printf("li ");
- ppHRegPPC(dst);
- vex_printf(",0x%x", (UInt)imm);
- } else {
- if (imm >=3D 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL) {
- // sign-extendable from 32 bits
- vex_printf("lis ");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 16));
- vex_printf("ori ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x", (UInt)(imm & 0xFFFF));
- } else {
- // full 64bit immediate load: 5 (five!) insns.
- vassert(mode64);
-
- // load high word
- vex_printf("lis ");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 48) & 0xFFFF);
- vex_printf("ori ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 32) & 0xFFFF);
- =20
- // shift r_dst low word to high word =3D> rldicr
- vex_printf("rldicr ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",32,31 ; ");
-
- // load low word
- vex_printf("oris ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 16) & 0xFFFF);
- vex_printf("ori ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x", (UInt)(imm >> 0) & 0xFFFF);
- }
- }
-#endif
}
=20
static void ppMovReg ( HReg dst, HReg src ) {
Modified: branches/AIX5/priv/host-ppc/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-ppc/hdefs.h 2006-09-29 22:26:57 UTC (rev 1665=
)
+++ branches/AIX5/priv/host-ppc/hdefs.h 2006-09-30 00:30:46 UTC (rev 1666=
)
@@ -838,7 +838,8 @@
extern PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bo=
ol mode64 );
extern PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bo=
ol mode64 );
extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 );
-extern HInstrArray* iselBB_PPC ( IRBB*, VexArchInfo*,
+extern HInstrArray* iselBB_PPC ( IRBB*, VexArch,
+ VexArchInfo*,
VexMiscInfo* );
=20
#endif /* ndef __LIBVEX_HOST_PPC_HDEFS_H */
Modified: branches/AIX5/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-ppc/isel.c 2006-09-29 22:26:57 UTC (rev 1665)
+++ branches/AIX5/priv/host-ppc/isel.c 2006-09-30 00:30:46 UTC (rev 1666)
@@ -3878,7 +3878,8 @@
=20
/* Translate an entire BB to ppc code. */
=20
-HInstrArray* iselBB_PPC ( IRBB* bb, VexArchInfo* archinfo_host,
+HInstrArray* iselBB_PPC ( IRBB* bb, VexArch arch_host,
+ VexArchInfo* archinfo_host,
VexMiscInfo* vmi )
{
Int i, j;
@@ -3886,33 +3887,24 @@
ISelEnv* env;
UInt hwcaps_host =3D archinfo_host->hwcaps;
Bool mode64 =3D False;
- Bool is32, is64;
UInt mask32, mask64;
=20
- /* Figure out whether we're being ppc32 or ppc64 today. */
+ vassert(arch_host =3D=3D VexArchPPC32 || arch_host =3D=3D VexArchPPC6=
4);
+ mode64 =3D arch_host =3D=3D VexArchPPC64;
+
+ /* do some sanity checks */
mask32 =3D VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V
| VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX;
=20
- is32 =3D (hwcaps_host & mask32) > 0;
-
mask64 =3D VEX_HWCAPS_PPC64_V
| VEX_HWCAPS_PPC64_FX | VEX_HWCAPS_PPC64_GX;
=20
- XXX this is a mess, fix me
if (mode64) {
vassert((hwcaps_host & mask32) =3D=3D 0);
} else {
vassert((hwcaps_host & mask64) =3D=3D 0);
}
- is64 =3D (hwcaps_host & mask64) > 0;
=20
- if (is32 && !is64)
- mode64 =3D False;
- else if (is64 && !is32)
- mode64 =3D True;
- else
- vpanic("iselBB_PPC: illegal subarch");
-
/* Make up an initial environment to use. */
env =3D LibVEX_Alloc(sizeof(ISelEnv));
env->vreg_ctr =3D 0;
Modified: branches/AIX5/priv/host-x86/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-x86/hdefs.h 2006-09-29 22:26:57 UTC (rev 1665=
)
+++ branches/AIX5/priv/host-x86/hdefs.h 2006-09-30 00:30:46 UTC (rev 1666=
)
@@ -665,7 +665,8 @@
extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool )=
;
extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool )=
;
extern void getAllocableRegs_X86 ( Int*, HReg** );
-extern HInstrArray* iselBB_X86 ( IRBB*, VexArchInfo*,
+extern HInstrArray* iselBB_X86 ( IRBB*, VexArch,
+ VexArchInfo*,
VexMiscInfo* );
=20
#endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */
Modified: branches/AIX5/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/host-x86/isel.c 2006-09-29 22:26:57 UTC (rev 1665)
+++ branches/AIX5/priv/host-x86/isel.c 2006-09-30 00:30:46 UTC (rev 1666)
@@ -3604,7 +3604,8 @@
=20
/* Translate an entire BB to x86 code. */
=20
-HInstrArray* iselBB_X86 ( IRBB* bb, VexArchInfo* archinfo_host,
+HInstrArray* iselBB_X86 ( IRBB* bb, VexArch arch_host,
+ VexArchInfo* archinfo_host,
VexMiscInfo* vmi/*UNUSED*/ )
{
Int i, j;
Modified: branches/AIX5/priv/main/vex_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/priv/main/vex_main.c 2006-09-29 22:26:57 UTC (rev 1665)
+++ branches/AIX5/priv/main/vex_main.c 2006-09-30 00:30:46 UTC (rev 1666)
@@ -193,7 +193,8 @@
HInstr* (*genReload) ( HReg, Int, Bool );
void (*ppInstr) ( HInstr*, Bool );
void (*ppReg) ( HReg );
- HInstrArray* (*iselBB) ( IRBB*, VexArchInfo*, VexMiscInfo* );
+ HInstrArray* (*iselBB) ( IRBB*, VexArch, VexArchInfo*,=20
+ VexMiscInfo* );
Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
IRExpr* (*specHelper) ( HChar*, IRExpr** );
Bool (*preciseMemExnsFn) ( Int, Int );
@@ -559,7 +560,8 @@
" Instruction selection "
"------------------------\n");
=20
- vcode =3D iselBB ( irbb, &vta->archinfo_host, &vta->miscinfo_both );
+ vcode =3D iselBB ( irbb, vta->arch_host, &vta->archinfo_host,=20
+ &vta->miscinfo_both );
=20
vexAllocSanityCheck();
=20
|