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From: <sv...@va...> - 2006-05-12 19:50:52
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Author: sewardj
Date: 2006-05-12 20:50:44 +0100 (Fri, 12 May 2006)
New Revision: 5892
Log:
Comprehensive tests for bt{s,r,c,}{w,l,q} on amd64.
Added:
trunk/memcheck/tests/amd64/bt_everything.c
trunk/memcheck/tests/amd64/bt_everything.stderr.exp
trunk/memcheck/tests/amd64/bt_everything.stdout.exp
trunk/memcheck/tests/amd64/bt_everything.vgtest
Modified:
trunk/memcheck/tests/amd64/Makefile.am
Modified: trunk/memcheck/tests/amd64/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/Makefile.am 2006-05-12 14:24:18 UTC (rev 5=
891)
+++ trunk/memcheck/tests/amd64/Makefile.am 2006-05-12 19:50:44 UTC (rev 5=
892)
@@ -8,10 +8,12 @@
$(addsuffix .stderr.exp,$(INSN_TESTS)) \
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
+ bt_everything.stderr.exp bt_everything.stdout.exp \
+ bt_everything.vgtest \
more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest
=20
-check_PROGRAMS =3D more_x87_fp sse_memory
+check_PROGRAMS =3D bt_everything more_x87_fp sse_memory
=20
AM_CPPFLAGS =3D -I$(top_srcdir)/include
AM_CFLAGS =3D $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/inc=
lude
Added: trunk/memcheck/tests/amd64/bt_everything.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/bt_everything.c (r=
ev 0)
+++ trunk/memcheck/tests/amd64/bt_everything.c 2006-05-12 19:50:44 UTC (r=
ev 5892)
@@ -0,0 +1,498 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+typedef unsigned short UShort;
+typedef unsigned char UChar;
+
+typedef signed int Int;
+typedef signed short Short;
+
+typedef signed long int Word;
+
+/* ------------ MEM, Q ------------ */
+
+ULong btsq_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btsq\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" (bitno));
+ /* Pretty meaningless to dereference base here, but that's what you
+ have to do to get a btsl insn which refers to memory starting at
+ base. */
+ return res;
+}
+
+ULong btrq_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btrq\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" (bitno));
+ return res;
+}
+
+ULong btcq_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btcq\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" (bitno));
+ return res;
+}
+
+ULong btq_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btq\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" (bitno)
+ : "cc", "memory");
+ return res;
+}
+
+
+/* ------------ MEM, L ------------ */
+
+ULong btsl_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btsl\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Int)bitno));
+ /* Pretty meaningless to dereference base here, but that's what you
+ have to do to get a btsl insn which refers to memory starting at
+ base. */
+ return res;
+}
+
+ULong btrl_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btrl\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Int)bitno));
+ return res;
+}
+
+ULong btcl_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btcl\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Int)bitno));
+ return res;
+}
+
+ULong btl_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btl\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Int)bitno)
+ : "cc", "memory");
+ return res;
+}
+
+
+
+/* ------------ MEM, W ------------ */
+
+ULong btsw_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btsw\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Short)bitno));
+ /* Pretty meaningless to dereference base here, but that's what you
+ have to do to get a btsl insn which refers to memory starting at
+ base. */
+ return res;
+}
+
+ULong btrw_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btrw\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Short)bitno));
+ return res;
+}
+
+ULong btcw_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btcw\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Short)bitno));
+ return res;
+}
+
+ULong btw_mem ( char* base, Word bitno )
+{
+ UChar res;
+ __asm__=20
+ __volatile__("btw\t%2, %0\n\t"
+ "setc\t%1"=20
+ : "=3Dm" (*base), "=3Dq" (res)
+ : "r" ((Short)bitno)
+ : "cc", "memory");
+ return res;
+}
+
+
+
+/* ------------ REG, Q ------------ */
+
+ULong btsq_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btsq\t%2, %%rax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" (bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btrq_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btrq\t%2, %%rax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" (bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btcq_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btcq\t%2, %%rax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" (bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btq_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btq\t%2, %%rax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" (bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+
+/* ------------ REG, L ------------ */
+
+ULong btsl_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btsl\t%2, %%eax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Int)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btrl_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btrl\t%2, %%eax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Int)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btcl_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btcl\t%2, %%eax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Int)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btl_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btl\t%2, %%eax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Int)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+
+/* ------------ REG, W ------------ */
+
+ULong btsw_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btsw\t%2, %%ax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Short)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btrw_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btrw\t%2, %%ax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Short)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btcw_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btcw\t%2, %%ax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Short)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+ULong btw_reg ( ULong reg_in, Word bitno,=20
+ ULong* reg_out_p )
+{
+ UChar res;
+ ULong reg_out;
+ __asm__=20
+ __volatile__("movq\t%3, %%rax\n\t"
+ "btw\t%2, %%ax\n\t"
+ "movq\t%%rax, %1\n\t"
+ "setc\t%0"=20
+ : "=3Dq" (res), "=3Dr" (reg_out)
+ : "r" ((Short)bitno), "r" (reg_in)
+ : "cc", "eax");
+ *reg_out_p =3D reg_out;
+ return res;
+}
+
+
+
+
+
+
+
+ULong rol1 ( ULong x )
+{
+ return (x << 1) | (x >> 63);
+}
+
+int main ( void )
+{
+ UInt n, op;
+ ULong carrydep, c, res;
+ UChar* block;
+ ULong reg;
+ Word bitoff;
+
+ /*------------------------ MEM-L -----------------------*/
+
+ carrydep =3D 0;
+ block =3D calloc(200,1);
+ block +=3D 100;
+ /* Valid bit offsets are -800 .. 799 inclusive. */
+
+ for (n =3D 0; n < 10000; n++) {
+ bitoff =3D (random() % 1600) - 800;
+ op =3D random() % 12;
+ c =3D 2;
+ switch (op) {
+ case 0: c =3D btsl_mem(block, bitoff); break;
+ case 1: c =3D btrl_mem(block, bitoff); break;
+ case 2: c =3D btcl_mem(block, bitoff); break;
+ case 3: c =3D btl_mem(block, bitoff); break;
+ case 4: c =3D btsq_mem(block, bitoff); break;
+ case 5: c =3D btrq_mem(block, bitoff); break;
+ case 6: c =3D btcq_mem(block, bitoff); break;
+ case 7: c =3D btq_mem(block, bitoff); break;
+ case 8: c =3D btsw_mem(block, bitoff); break;
+ case 9: c =3D btrw_mem(block, bitoff); break;
+ case 10: c =3D btcw_mem(block, bitoff); break;
+ case 11: c =3D btw_mem(block, bitoff); break;
+ default: assert(0);
+ }
+ assert(c =3D=3D 0 || c =3D=3D 1);
+ carrydep =3D c ? (rol1(carrydep) ^ bitoff) : carrydep;
+ }
+
+ /* Compute final result */
+ block -=3D 100; =20
+ res =3D 0;
+ for (n =3D 0; n < 200; n++) {
+ UChar ch =3D block[n];
+ /* printf("%d ", (int)block[n]); */
+ res =3D rol1(res) ^ (UInt)ch;
+ }
+
+ printf("MEM-L: final res 0x%llx, carrydep 0x%llx\n", res, carrydep);
+
+ /*------------------------ REG-L -----------------------*/
+
+ carrydep =3D 0;
+ reg =3D 0;
+
+ for (n =3D 0; n < 1000; n++) {
+ bitoff =3D (random() % 100) - 50;
+ op =3D random() % 12;
+ c =3D 2;
+ switch (op) {
+ case 0: c =3D btsl_reg(reg, bitoff, ®); break;
+ case 1: c =3D btrl_reg(reg, bitoff, ®); break;
+ case 2: c =3D btcl_reg(reg, bitoff, ®); break;
+ case 3: c =3D btl_reg(reg, bitoff, ®); break;
+ case 4: c =3D btsq_reg(reg, bitoff, ®); break;
+ case 5: c =3D btrq_reg(reg, bitoff, ®); break;
+ case 6: c =3D btcq_reg(reg, bitoff, ®); break;
+ case 7: c =3D btq_reg(reg, bitoff, ®); break;
+ case 8: c =3D btsw_reg(reg, bitoff, ®); break;
+ case 9: c =3D btrw_reg(reg, bitoff, ®); break;
+ case 10: c =3D btcw_reg(reg, bitoff, ®); break;
+ case 11: c =3D btw_reg(reg, bitoff, ®); break;
+ default: assert(0);
+ }
+ assert(c =3D=3D 0 || c =3D=3D 1);
+ carrydep =3D c ? (rol1(carrydep) ^ bitoff) : carrydep;
+ }
+
+ printf("REG-L: final res 0x%llx, carrydep 0x%llx\n", reg, carrydep);
+
+ block +=3D 100;
+
+ /* Just try one of these at once; more than one can cause a
+ confusing merging of error messages. */
+ //btsl_mem(block, -800); /* should not complain */
+ //btsl_mem(block, -801); /* should complain */
+ //btsl_mem(block, 799); /* should not complain */
+ //btsl_mem(block, 800); /* should complain */
+
+ block -=3D 100;
+ free(block);
+
+ return 0;
+}
+
Added: trunk/memcheck/tests/amd64/bt_everything.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Added: trunk/memcheck/tests/amd64/bt_everything.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/bt_everything.stdout.exp =
(rev 0)
+++ trunk/memcheck/tests/amd64/bt_everything.stdout.exp 2006-05-12 19:50:=
44 UTC (rev 5892)
@@ -0,0 +1,2 @@
+MEM-L: final res 0xbb05dc8f69ba36dc, carrydep 0x818f336625f01277
+REG-L: final res 0xa15f293e, carrydep 0x6082b5e5befc6a40
Added: trunk/memcheck/tests/amd64/bt_everything.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/bt_everything.vgtest =
(rev 0)
+++ trunk/memcheck/tests/amd64/bt_everything.vgtest 2006-05-12 19:50:44 U=
TC (rev 5892)
@@ -0,0 +1,2 @@
+prog: bt_everything
+vgopts: -q
|