|
From: <sv...@va...> - 2006-05-12 14:04:55
|
Author: sewardj
Date: 2006-05-12 15:04:48 +0100 (Fri, 12 May 2006)
New Revision: 1611
Log:
Support 'popw m16'. Fixes #126243.
Modified:
trunk/priv/guest-x86/toIR.c
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2006-05-06 14:40:40 UTC (rev 1610)
+++ trunk/priv/guest-x86/toIR.c 2006-05-12 14:04:48 UTC (rev 1611)
@@ -11467,19 +11467,23 @@
break;
=20
case 0x8F: /* POPL/POPW m32 */
- { Int len;
- UChar rm =3D getIByte(delta);
+ { Int len;
+ UChar rm =3D getIByte(delta);
=20
/* make sure this instruction is correct POP */
- vassert(!epartIsReg(rm) && (gregOfRM(rm) =3D=3D 0));
+ if (epartIsReg(rm) || gregOfRM(rm) !=3D 0)
+ goto decode_failure;
/* and has correct size */
- vassert(sz =3D=3D 4); =20
- =20
- t1 =3D newTemp(Ity_I32); t3 =3D newTemp(Ity_I32);
+ if (sz !=3D 4 && sz !=3D 2)
+ goto decode_failure;
+ ty =3D szToITy(sz);
+
+ t1 =3D newTemp(Ity_I32); /* stack address */
+ t3 =3D newTemp(ty); /* data */
/* set t1 to ESP: t1 =3D ESP */
assign( t1, getIReg(4, R_ESP) );
/* load M[ESP] to virtual register t3: t3 =3D M[t1] */
- assign( t3, loadLE(Ity_I32, mkexpr(t1)) );
+ assign( t3, loadLE(ty, mkexpr(t1)) );
=20
/* increase ESP; must be done before the STORE. Intel manual say=
s:
If the ESP register is used as a base register for addressin=
g
@@ -11493,7 +11497,7 @@
addr =3D disAMode ( &len, sorb, delta, dis_buf);
storeLE( mkexpr(addr), mkexpr(t3) );
=20
- DIP("popl %s\n", dis_buf);
+ DIP("pop%c %s\n", sz=3D=3D2 ? 'w' : 'l', dis_buf);
=20
delta +=3D len;
break;
|