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From: <sv...@va...> - 2006-05-01 02:14:38
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Author: sewardj
Date: 2006-05-01 03:14:17 +0100 (Mon, 01 May 2006)
New Revision: 1606
Log:
Counterpart to r1605: in the ppc insn selector, don't use the bits
VexArchInfo.hwcaps to distinguish ppc32 and ppc64. Instead pass
the host arch around. And associated plumbing.
Modified:
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
trunk/priv/host-ppc/hdefs.h
trunk/priv/host-ppc/isel.c
trunk/priv/host-x86/hdefs.h
trunk/priv/host-x86/isel.c
trunk/priv/main/vex_main.c
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/host-amd64/hdefs.h 2006-05-01 02:14:17 UTC (rev 1606)
@@ -718,7 +718,7 @@
extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool=
);
extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool=
);
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
-extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArchInfo* );
+extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArch, VexArchInfo=
* );
=20
#endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */
=20
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/host-amd64/isel.c 2006-05-01 02:14:17 UTC (rev 1606)
@@ -3760,7 +3760,8 @@
=20
/* Translate an entire BB to amd64 code. */
=20
-HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArchInfo* archinfo_host )
+HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArch arch_host,
+ VexArchInfo* archinfo_host )
{
Int i, j;
HReg hreg, hregHI;
@@ -3768,6 +3769,7 @@
UInt hwcaps_host =3D archinfo_host->hwcaps;
=20
/* sanity ... */
+ vassert(arch_host =3D=3D VexArchAMD64);
vassert(0 =3D=3D (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3)));
=20
/* Make up an initial environment to use. */
Modified: trunk/priv/host-ppc/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.h 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/host-ppc/hdefs.h 2006-05-01 02:14:17 UTC (rev 1606)
@@ -838,7 +838,7 @@
extern PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bo=
ol mode64 );
extern PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bo=
ol mode64 );
extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 );
-extern HInstrArray* iselBB_PPC ( IRBB*, VexArchInfo* );
+extern HInstrArray* iselBB_PPC ( IRBB*, VexArch, VexArchInfo* =
);
=20
#endif /* ndef __LIBVEX_HOST_PPC_HDEFS_H */
=20
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/host-ppc/isel.c 2006-05-01 02:14:17 UTC (rev 1606)
@@ -3839,34 +3839,32 @@
=20
/* Translate an entire BB to ppc code. */
=20
-HInstrArray* iselBB_PPC ( IRBB* bb, VexArchInfo* archinfo_host )
+HInstrArray* iselBB_PPC ( IRBB* bb, VexArch arch_host,
+ VexArchInfo* archinfo_host )
{
Int i, j;
HReg hreg, hregHI;
ISelEnv* env;
UInt hwcaps_host =3D archinfo_host->hwcaps;
Bool mode64 =3D False;
- Bool is32, is64;
UInt mask32, mask64;
=20
- /* Figure out whether we're being ppc32 or ppc64 today. */
+ vassert(arch_host =3D=3D VexArchPPC32 || arch_host =3D=3D VexArchPPC6=
4);
+ mode64 =3D arch_host =3D=3D VexArchPPC64;
+
+ /* do some sanity checks */
mask32 =3D VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V
| VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX;
=20
- is32 =3D (hwcaps_host & mask32) > 0;
-
mask64 =3D VEX_HWCAPS_PPC64_V
| VEX_HWCAPS_PPC64_FX | VEX_HWCAPS_PPC64_GX;
=20
- is64 =3D (hwcaps_host & mask64) > 0;
+ if (mode64) {
+ vassert((hwcaps_host & mask32) =3D=3D 0);
+ } else {
+ vassert((hwcaps_host & mask64) =3D=3D 0);
+ }
=20
- if (is32 && !is64)
- mode64 =3D False;
- else if (is64 && !is32)
- mode64 =3D True;
- else
- vpanic("iselBB_PPC: illegal subarch");
-
/* Make up an initial environment to use. */
env =3D LibVEX_Alloc(sizeof(ISelEnv));
env->vreg_ctr =3D 0;
Modified: trunk/priv/host-x86/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/hdefs.h 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/host-x86/hdefs.h 2006-05-01 02:14:17 UTC (rev 1606)
@@ -665,7 +665,7 @@
extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool )=
;
extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool )=
;
extern void getAllocableRegs_X86 ( Int*, HReg** );
-extern HInstrArray* iselBB_X86 ( IRBB*, VexArchInfo* );
+extern HInstrArray* iselBB_X86 ( IRBB*, VexArch, VexArchInfo* =
);
=20
#endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */
=20
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/host-x86/isel.c 2006-05-01 02:14:17 UTC (rev 1606)
@@ -3604,7 +3604,8 @@
=20
/* Translate an entire BB to x86 code. */
=20
-HInstrArray* iselBB_X86 ( IRBB* bb, VexArchInfo* archinfo_host )
+HInstrArray* iselBB_X86 ( IRBB* bb, VexArch arch_host,
+ VexArchInfo* archinfo_host )
{
Int i, j;
HReg hreg, hregHI;
@@ -3612,6 +3613,7 @@
UInt hwcaps_host =3D archinfo_host->hwcaps;
=20
/* sanity ... */
+ vassert(arch_host =3D=3D VexArchX86);
vassert(0 =3D=3D (hwcaps_host & ~(VEX_HWCAPS_X86_SSE1
|VEX_HWCAPS_X86_SSE2
|VEX_HWCAPS_X86_SSE3)));
Modified: trunk/priv/main/vex_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/main/vex_main.c 2006-04-30 23:37:32 UTC (rev 1605)
+++ trunk/priv/main/vex_main.c 2006-05-01 02:14:17 UTC (rev 1606)
@@ -193,7 +193,7 @@
HInstr* (*genReload) ( HReg, Int, Bool );
void (*ppInstr) ( HInstr*, Bool );
void (*ppReg) ( HReg );
- HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* );
+ HInstrArray* (*iselBB) ( IRBB*, VexArch, VexArchInfo* );
Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
IRExpr* (*specHelper) ( HChar*, IRExpr** );
Bool (*preciseMemExnsFn) ( Int, Int );
@@ -558,7 +558,7 @@
" Instruction selection "
"------------------------\n");
=20
- vcode =3D iselBB ( irbb, &vta->archinfo_host );
+ vcode =3D iselBB ( irbb, vta->arch_host, &vta->archinfo_host );
=20
vexAllocSanityCheck();
=20
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