|
From: <sv...@va...> - 2006-03-07 00:25:06
|
Author: sewardj
Date: 2006-03-07 00:24:59 +0000 (Tue, 07 Mar 2006)
New Revision: 1592
Log:
Merge r1591 (Implement fnstsw).
Modified:
branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-07 00:22:02 U=
TC (rev 1591)
+++ branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-07 00:24:59 U=
TC (rev 1592)
@@ -4172,7 +4172,23 @@
put_C3210( binop(Iop_And64, get_C3210(), mkU64(~AMD64G_FC_MASK_C2)) )=
;
}
=20
+/* Invent a plausible-looking FPU status word value:
+ ((ftop & 7) << 11) | (c3210 & 0x4700)
+ */
+static IRExpr* get_FPU_sw ( void )
+{
+ return
+ unop(Iop_32to16,
+ binop(Iop_Or32,
+ binop(Iop_Shl32,=20
+ binop(Iop_And32, get_ftop(), mkU32(7)),=20
+ mkU8(11)),
+ binop(Iop_And32, unop(Iop_64to32, get_C3210()),=20
+ mkU32(0x4700))
+ ));
+}
=20
+
/* ------------------------------------------------------- */
/* Given all that stack-mangling junk, we can now go ahead
and describe FP instructions.=20
@@ -5423,6 +5439,14 @@
//.. break;
//.. }
=20
+ case 7: { /* FNSTSW m16 */
+ IRExpr* sw =3D get_FPU_sw();
+ vassert(typeOfIRExpr(irbb->tyenv, sw) =3D=3D Ity_I16);
+ storeLE( mkexpr(addr), sw );
+ DIP("fnstsw %s\n", dis_buf);
+ break;
+ }
+
default:
vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
vex_printf("first_opcode =3D=3D 0xDD\n");
|