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From: <sv...@va...> - 2006-03-06 20:04:06
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Author: sewardj
Date: 2006-03-06 20:03:43 +0000 (Mon, 06 Mar 2006)
New Revision: 1590
Log:
Merge r1533 (Implement clflush).
Modified:
branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-06 19:23:30 U=
TC (rev 1589)
+++ branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-06 20:03:43 U=
TC (rev 1590)
@@ -395,6 +395,8 @@
#define OFFB_XMM15 offsetof(VexGuestAMD64State,guest_XMM15)
=20
#define OFFB_EMWARN offsetof(VexGuestAMD64State,guest_EMWARN)
+#define OFFB_TISTART offsetof(VexGuestAMD64State,guest_TISTART)
+#define OFFB_TILEN offsetof(VexGuestAMD64State,guest_TILEN)
=20
=20
/*------------------------------------------------------------*/
@@ -11417,25 +11419,40 @@
//.. //-- DIP("fx%s %s\n", store ? "save" : "rstor", dis_buf );
//.. //-- goto decode_success;
//.. //-- }
-//.. //--=20
-//.. //-- /* CLFLUSH -- flush cache line */
-//.. //-- if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
-//.. //-- && (!epartIsReg(insn[2]))
-//.. //-- && (gregOfRM(insn[2]) =3D=3D 7))
-//.. //-- {
-//.. //-- vg_assert(sz =3D=3D 4);
-//.. //-- pair =3D disAMode ( cb, sorb, eip+2, dis_buf );
-//.. //-- t1 =3D LOW24(pair);
-//.. //-- eip +=3D 2+HI8(pair);
-//.. //-- uInstr3(cb, SSE2a_MemRd, 0, /* ignore sz for internal o=
ps */
-//.. //-- Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
-//.. //-- Lit16, (UShort)insn[2],
-//.. //-- TempReg, t1 );
-//.. //-- DIP("clflush %s\n", dis_buf);
-//.. //-- goto decode_success;
-//.. //-- }
=20
+ /* 0F AE /7 =3D CLFLUSH -- flush cache line */
+ if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
+ && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) =3D=3D 7) {
=20
+ /* This is something of a hack. We need to know the size of the
+ cache line containing addr. Since we don't (easily), assume
+ 256 on the basis that no real cache would have a line that
+ big. It's safe to invalidate more stuff than we need, just
+ inefficient. */
+ ULong lineszB =3D 256ULL;
+
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+
+ /* Round addr down to the start of the containing block. */
+ stmt( IRStmt_Put(
+ OFFB_TISTART,
+ binop( Iop_And64,=20
+ mkexpr(addr),=20
+ mkU64( ~(lineszB-1) ))) );
+
+ stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) );
+
+ irbb->jumpkind =3D Ijk_TInval;
+ irbb->next =3D mkU64(guest_RIP_bbstart+delta);
+ dres.whatNext =3D Dis_StopHere;
+
+ DIP("clflush %s\n", dis_buf);
+ goto decode_success;
+ }
+
+
/* ---------------------------------------------------- */
/* --- end of the SSE/SSE2 decoder. --- */
/* ---------------------------------------------------- */
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