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From: <sv...@va...> - 2006-02-21 17:43:26
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Author: sewardj
Date: 2006-02-21 17:43:20 +0000 (Tue, 21 Feb 2006)
New Revision: 1575
Log:
Re-enable 'fsqrt'. This isn't really correct in the sense that the
insn is allowed even if the CPU doesn't support it. No matter; it
is done properly in the svn trunk (to become 3.2.0).
Modified:
branches/VEX_3_1_BRANCH/priv/guest-ppc32/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-ppc32/toIR.c 2006-02-09 02:54:03 U=
TC (rev 1574)
+++ branches/VEX_3_1_BRANCH/priv/guest-ppc32/toIR.c 2006-02-21 17:43:20 U=
TC (rev 1575)
@@ -4419,15 +4419,15 @@
assign( frD, binop( Iop_AddF64, mkexpr(frA), mkexpr(frB) ) );
break;
=20
-//zz case 0x16: // fsqrt (Floating SqRt (Double-Precision), PPC32 =
p427)
-//zz if (frA_addr !=3D 0 || frC_addr !=3D 0) {
-//zz vex_printf("dis_fp_arith(PPC32)(instr,fsqrt)\n");
-//zz return False;
-//zz }
-//zz DIP("fsqrt%s fr%d,fr%d\n", flag_rC ? "." : "",
-//zz frD_addr, frB_addr);
-//zz assign( frD, unop( Iop_SqrtF64, mkexpr(frB) ) );
-//zz break;
+ case 0x16: // fsqrt (Floating SqRt (Double-Precision), PPC32 p427)
+ if (frA_addr !=3D 0 || frC_addr !=3D 0) {
+ vex_printf("dis_fp_arith(PPC32)(instr,fsqrt)\n");
+ return False;
+ }
+ DIP("fsqrt%s fr%d,fr%d\n", flag_rC ? "." : "",
+ frD_addr, frB_addr);
+ assign( frD, unop( Iop_SqrtF64, mkexpr(frB) ) );
+ break;
=20
case 0x17: { // fsel (Floating Select, PPC32 p426)
IRTemp cc =3D newTemp(Ity_I32);
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