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From: <sv...@va...> - 2006-02-17 10:56:48
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Author: njn
Date: 2006-02-17 10:56:34 +0000 (Fri, 17 Feb 2006)
New Revision: 5654
Log:
Rename V_BITS*_{VALID,INVALID} as V_BITS*_{DEFINED,UNDEFINED}, which is
clearer.
Modified:
branches/COMPVBITS/memcheck/mc_include.h
branches/COMPVBITS/memcheck/mc_main.c
branches/COMPVBITS/memcheck/mc_translate.c
Modified: branches/COMPVBITS/memcheck/mc_include.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/COMPVBITS/memcheck/mc_include.h 2006-02-15 10:45:18 UTC (rev=
5653)
+++ branches/COMPVBITS/memcheck/mc_include.h 2006-02-17 10:56:34 UTC (rev=
5654)
@@ -177,20 +177,20 @@
#define SM_SIZE 65536 /* DO NOT CHANGE */
#define SM_MASK (SM_SIZE-1) /* DO NOT CHANGE */
=20
-#define V_BIT_VALID 0
-#define V_BIT_INVALID 1
+#define V_BIT_DEFINED 0
+#define V_BIT_UNDEFINED 1
=20
-#define V_BITS8_VALID 0
-#define V_BITS8_INVALID 0xFF
+#define V_BITS8_DEFINED 0
+#define V_BITS8_UNDEFINED 0xFF
=20
-#define V_BITS16_VALID 0
-#define V_BITS16_INVALID 0xFFFF
+#define V_BITS16_DEFINED 0
+#define V_BITS16_UNDEFINED 0xFFFF
=20
-#define V_BITS32_VALID 0
-#define V_BITS32_INVALID 0xFFFFFFFF
+#define V_BITS32_DEFINED 0
+#define V_BITS32_UNDEFINED 0xFFFFFFFF
=20
-#define V_BITS64_VALID 0ULL
-#define V_BITS64_INVALID 0xFFFFFFFFFFFFFFFFULL
+#define V_BITS64_DEFINED 0ULL
+#define V_BITS64_UNDEFINED 0xFFFFFFFFFFFFFFFFULL
=20
=20
/*------------------------------------------------------------*/
Modified: branches/COMPVBITS/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/COMPVBITS/memcheck/mc_main.c 2006-02-15 10:45:18 UTC (rev 56=
53)
+++ branches/COMPVBITS/memcheck/mc_main.c 2006-02-17 10:56:34 UTC (rev 56=
54)
@@ -566,10 +566,10 @@
// Addressable. Convert in-register format to in-memory format.
// Also remove any existing sec V bit entry for the byte if no
// longer necessary.
- if ( V_BITS8_VALID =3D=3D vbits8 ) { vabits2 =3D VA_BITS2_R=
EADABLE; }
- else if ( V_BITS8_INVALID =3D=3D vbits8 ) { vabits2 =3D VA_BITS2_W=
RITABLE; }
- else { vabits2 =3D VA_BITS2_OTHER=
;
- set_sec_vbits8(a, vbits8);=
}
+ if ( V_BITS8_DEFINED =3D=3D vbits8 ) { vabits2 =3D VA_BITS2=
_READABLE; }
+ else if ( V_BITS8_UNDEFINED =3D=3D vbits8 ) { vabits2 =3D VA_BITS2=
_WRITABLE; }
+ else { vabits2 =3D VA_BITS2_OTH=
ER;
+ set_sec_vbits8(a, vbits8=
); }
set_vabits2(a, vabits2);
=20
} else {
@@ -590,10 +590,10 @@
UChar vabits2 =3D get_vabits2(a);
=20
// Convert the in-memory format to in-register format.
- if ( VA_BITS2_READABLE =3D=3D vabits2 ) { *vbits8 =3D V_BITS8_VA=
LID; }
- else if ( VA_BITS2_WRITABLE =3D=3D vabits2 ) { *vbits8 =3D V_BITS8_IN=
VALID; }
+ if ( VA_BITS2_READABLE =3D=3D vabits2 ) { *vbits8 =3D V_BITS8_DE=
FINED; }
+ else if ( VA_BITS2_WRITABLE =3D=3D vabits2 ) { *vbits8 =3D V_BITS8_UN=
DEFINED; }
else if ( VA_BITS2_NOACCESS =3D=3D vabits2 ) {
- *vbits8 =3D V_BITS8_VALID; // Make V bits defined!
+ *vbits8 =3D V_BITS8_DEFINED; // Make V bits defined!
ok =3D False;
} else {
tl_assert( VA_BITS2_OTHER =3D=3D vabits2 );
@@ -758,7 +758,7 @@
// Shouldn't be fully defined or fully undefined -- those cases shoul=
dn't
// make it to the secondary V bits table.
vbits8 =3D n->vbits8[amod];
- tl_assert(V_BITS8_VALID !=3D vbits8 && V_BITS8_INVALID !=3D vbits8);
+ tl_assert(V_BITS8_DEFINED !=3D vbits8 && V_BITS8_UNDEFINED !=3D vbits=
8);
return vbits8;
}
=20
@@ -769,7 +769,7 @@
SecVBitNode* n =3D VG_(OSet_Lookup)(secVBitTable, &aAligned);
// Shouldn't be fully defined or fully undefined -- those cases shoul=
dn't
// make it to the secondary V bits table.
- tl_assert(V_BITS8_VALID !=3D vbits8 && V_BITS8_INVALID !=3D vbits8);
+ tl_assert(V_BITS8_DEFINED !=3D vbits8 && V_BITS8_UNDEFINED !=3D vbits=
8);
if (n) {
n->vbits8[amod] =3D vbits8; // update
n->last_touched =3D GCs_done;
@@ -780,7 +780,7 @@
n =3D VG_(OSet_AllocNode)(secVBitTable, sizeof(SecVBitNode));
n->a =3D aAligned;
for (i =3D 0; i < BYTES_PER_SEC_VBIT_NODE; i++) {
- n->vbits8[i] =3D V_BITS8_INVALID;
+ n->vbits8[i] =3D V_BITS8_UNDEFINED;
}
n->vbits8[amod] =3D vbits8;
n->last_touched =3D GCs_done;
@@ -826,7 +826,7 @@
valid addresses and Defined for invalid addresses. Iterate over
the bytes in the word, from the most significant down to the
least. */
- ULong vbits64 =3D V_BITS64_INVALID;
+ ULong vbits64 =3D V_BITS64_UNDEFINED;
SSizeT i =3D szB-1; // Must be signed
SizeT n_addrs_bad =3D 0;
Addr ai;
@@ -1793,7 +1793,7 @@
{
UChar area[1024];
tl_assert(size <=3D 1024);
- VG_(memset)(area, V_BITS8_VALID, size);
+ VG_(memset)(area, V_BITS8_DEFINED, size);
VG_(set_shadow_regs_area)( tid, offset, size, area );
}
=20
@@ -1822,7 +1822,7 @@
=20
bad =3D False;
for (i =3D 0; i < size; i++) {
- if (area[i] !=3D V_BITS8_VALID) {
+ if (area[i] !=3D V_BITS8_DEFINED) {
bad =3D True;
break;
}
@@ -2728,9 +2728,9 @@
// addressible.
// Convert V bits from compact memory form to expanded register form.
if (EXPECTED_TAKEN(vabits16 =3D=3D VA_BITS16_READABLE)) {
- return V_BITS64_VALID;
+ return V_BITS64_DEFINED;
} else if (EXPECTED_TAKEN(vabits16 =3D=3D VA_BITS16_WRITABLE)) {
- return V_BITS64_INVALID;
+ return V_BITS64_UNDEFINED;
} else {
/* Slow case: the 8 bytes are not all-readable or all-writable. */
PROF_EVENT(202, "mc_LOADV8-slow2");
@@ -2779,9 +2779,9 @@
/* Handle common case quickly: a is suitably aligned, */
/* is mapped, and is addressible. */
// Convert full V-bits in register to compact 2-bit form.
- if (V_BITS64_VALID =3D=3D vbytes) {
+ if (V_BITS64_DEFINED =3D=3D vbytes) {
((UShort*)(sm->vabits8))[sm_off16] =3D (UShort)VA_BITS16_READAB=
LE;
- } else if (V_BITS64_INVALID =3D=3D vbytes) {
+ } else if (V_BITS64_UNDEFINED =3D=3D vbytes) {
((UShort*)(sm->vabits8))[sm_off16] =3D (UShort)VA_BITS16_WRITAB=
LE;
} else {
/* Slow but general case -- writing partially defined bytes. */
@@ -2834,9 +2834,9 @@
// For 64-bit platforms, set the high 32 bits of retval to 1 (undefin=
ed).
// Almost certainly not necessary, but be paranoid.
if (EXPECTED_TAKEN(vabits8 =3D=3D VA_BITS8_READABLE)) {
- return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_VALID);
+ return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_DEFINED);
} else if (EXPECTED_TAKEN(vabits8 =3D=3D VA_BITS8_WRITABLE)) {
- return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_INVALID);
+ return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_UNDEFINED);
} else {
/* Slow case: the 4 bytes are not all-readable or all-writable. */
PROF_EVENT(222, "mc_LOADV4-slow2");
@@ -2881,7 +2881,7 @@
// Cleverness: sometimes we don't have to write the shadow memory at
// all, if we can tell that what we want to write is the same as what=
is
// already there.
- if (V_BITS32_VALID =3D=3D vbytes) {
+ if (V_BITS32_DEFINED =3D=3D vbytes) {
if (vabits8 =3D=3D (UInt)VA_BITS8_READABLE) {
return;
} else if (!is_distinguished_sm(sm) && VA_BITS8_WRITABLE =3D=3D va=
bits8) {
@@ -2891,7 +2891,7 @@
PROF_EVENT(232, "mc_STOREV4-slow2");
mc_STOREVn_slow( a, 4, (ULong)vbytes, isBigEndian );
}
- } else if (V_BITS32_INVALID =3D=3D vbytes) {
+ } else if (V_BITS32_UNDEFINED =3D=3D vbytes) {
if (vabits8 =3D=3D (UInt)VA_BITS8_WRITABLE) {
return;
} else if (!is_distinguished_sm(sm) && VA_BITS8_READABLE =3D=3D va=
bits8) {
@@ -2915,9 +2915,9 @@
/* Handle common case quickly: a is suitably aligned, */
/* is mapped, and is addressible. */
// Convert full V-bits in register to compact 2-bit form.
- if (V_BITS32_VALID =3D=3D vbytes) {
+ if (V_BITS32_DEFINED =3D=3D vbytes) {
sm->vabits8[sm_off] =3D VA_BITS8_READABLE;
- } else if (V_BITS32_INVALID =3D=3D vbytes) {
+ } else if (V_BITS32_UNDEFINED =3D=3D vbytes) {
sm->vabits8[sm_off] =3D VA_BITS8_WRITABLE;
} else {
/* Slow but general case -- writing partially defined bytes. */
@@ -2969,14 +2969,14 @@
// addressible.
// Convert V bits from compact memory form to expanded register form
// XXX: set the high 16/48 bits of retval to 1 for 64-bit paranoia?
- if (vabits8 =3D=3D VA_BITS8_READABLE) { return V_BITS16_VALID; =
}
- else if (vabits8 =3D=3D VA_BITS8_WRITABLE) { return V_BITS16_INVALID;=
}
+ if (vabits8 =3D=3D VA_BITS8_READABLE) { return V_BITS16_DEFINED;=
}
+ else if (vabits8 =3D=3D VA_BITS8_WRITABLE) { return V_BITS16_UNDEFINE=
D; }
else {
// The 4 (yes, 4) bytes are not all-readable or all-writable, chec=
k
// the two sub-bytes.
UChar vabits4 =3D extract_vabits4_from_vabits8(a, vabits8);
- if (vabits4 =3D=3D VA_BITS4_READABLE) { return V_BITS16_VALID=
; }
- else if (vabits4 =3D=3D VA_BITS4_WRITABLE) { return V_BITS16_INVAL=
ID; }
+ if (vabits4 =3D=3D VA_BITS4_READABLE) { return V_BITS16_DEFIN=
ED; }
+ else if (vabits4 =3D=3D VA_BITS4_WRITABLE) { return V_BITS16_UNDEF=
INED; }
else {
/* Slow case: the two bytes are not all-readable or all-writabl=
e. */
PROF_EVENT(242, "mc_LOADV2-slow2");
@@ -3023,10 +3023,10 @@
/* Handle common case quickly: a is suitably aligned, */
/* is mapped, and is addressible. */
// Convert full V-bits in register to compact 2-bit form.
- if (V_BITS16_VALID =3D=3D vbytes) {
+ if (V_BITS16_DEFINED =3D=3D vbytes) {
insert_vabits4_into_vabits8( a, VA_BITS4_READABLE,
&(sm->vabits8[sm_off]) );
- } else if (V_BITS16_INVALID =3D=3D vbytes) {
+ } else if (V_BITS16_UNDEFINED =3D=3D vbytes) {
insert_vabits4_into_vabits8( a, VA_BITS4_WRITABLE,
&(sm->vabits8[sm_off]) );
} else {
@@ -3078,14 +3078,14 @@
// Handle common case quickly: a is mapped, and the entire
// word32 it lives in is addressible.
// XXX: set the high 24/56 bits of retval to 1 for 64-bit paranoia?
- if (vabits8 =3D=3D VA_BITS8_READABLE) { return V_BITS8_VALID; =
}
- else if (vabits8 =3D=3D VA_BITS8_WRITABLE) { return V_BITS8_INVALID; =
}
+ if (vabits8 =3D=3D VA_BITS8_READABLE) { return V_BITS8_DEFINED; =
}
+ else if (vabits8 =3D=3D VA_BITS8_WRITABLE) { return V_BITS8_UNDEFINED=
; }
else {
// The 4 (yes, 4) bytes are not all-readable or all-writable, chec=
k
// the single byte.
UChar vabits2 =3D extract_vabits2_from_vabits8(a, vabits8);
- if (vabits2 =3D=3D VA_BITS2_READABLE) { return V_BITS8_VALID;=
}
- else if (vabits2 =3D=3D VA_BITS2_WRITABLE) { return V_BITS8_INVALI=
D; }
+ if (vabits2 =3D=3D VA_BITS2_READABLE) { return V_BITS8_DEFINE=
D; }
+ else if (vabits2 =3D=3D VA_BITS2_WRITABLE) { return V_BITS8_UNDEFI=
NED; }
else {
/* Slow case: the byte is not all-readable or all-writable. */
PROF_EVENT(262, "mc_LOADV1-slow2");
@@ -3123,10 +3123,10 @@
/* Handle common case quickly: a is mapped, the entire word32 it
lives in is addressible. */
// Convert full V-bits in register to compact 2-bit form.
- if (V_BITS8_VALID =3D=3D vbyte) {
+ if (V_BITS8_DEFINED =3D=3D vbyte) {
insert_vabits2_into_vabits8( a, VA_BITS2_READABLE,
&(sm->vabits8[sm_off]) );
- } else if (V_BITS8_INVALID =3D=3D vbyte) {
+ } else if (V_BITS8_UNDEFINED =3D=3D vbyte) {
insert_vabits2_into_vabits8( a, VA_BITS2_WRITABLE,
&(sm->vabits8[sm_off]) );
} else {
@@ -3228,7 +3228,7 @@
ok =3D get_vbits8(a + i, &vbits8);
tl_assert(ok);
// XXX: used to do this, but it's a pain
-// if (V_BITS8_VALID !=3D vbits8)
+// if (V_BITS8_DEFINED !=3D vbits8)
// mc_record_value_error(tid, 1);
((UChar*)vbits)[i] =3D vbits8;
}
@@ -3303,10 +3303,10 @@
Int i;
SecMap* sm;
=20
- tl_assert(V_BIT_INVALID =3D=3D 1);
- tl_assert(V_BIT_VALID =3D=3D 0);
- tl_assert(V_BITS8_INVALID =3D=3D 0xFF);
- tl_assert(V_BITS8_VALID =3D=3D 0);
+ tl_assert(V_BIT_UNDEFINED =3D=3D 1);
+ tl_assert(V_BIT_DEFINED =3D=3D 0);
+ tl_assert(V_BITS8_UNDEFINED =3D=3D 0xFF);
+ tl_assert(V_BITS8_DEFINED =3D=3D 0);
=20
/* Build the 3 distinguished secondaries */
sm =3D &sm_distinguished[SM_DIST_NOACCESS];
Modified: branches/COMPVBITS/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/COMPVBITS/memcheck/mc_translate.c 2006-02-15 10:45:18 UTC (r=
ev 5653)
+++ branches/COMPVBITS/memcheck/mc_translate.c 2006-02-17 10:56:34 UTC (r=
ev 5654)
@@ -2528,11 +2528,11 @@
// shadow computation ops that precede it.
if (!MC_(clo_undef_value_errors)) {
switch (ty) {
- case Ity_V128: c =3D IRConst_V128(V_BITS16_VALID); break; // V1=
28 weirdness
- case Ity_I64: c =3D IRConst_U64 (V_BITS64_VALID); break;
- case Ity_I32: c =3D IRConst_U32 (V_BITS32_VALID); break;
- case Ity_I16: c =3D IRConst_U16 (V_BITS16_VALID); break;
- case Ity_I8: c =3D IRConst_U8 (V_BITS8_VALID); break;
+ case Ity_V128: c =3D IRConst_V128(V_BITS16_DEFINED); break; // =
V128 weirdness
+ case Ity_I64: c =3D IRConst_U64 (V_BITS64_DEFINED); break;
+ case Ity_I32: c =3D IRConst_U32 (V_BITS32_DEFINED); break;
+ case Ity_I16: c =3D IRConst_U16 (V_BITS16_DEFINED); break;
+ case Ity_I8: c =3D IRConst_U8 (V_BITS8_DEFINED); break;
default: VG_(tool_panic)("memcheck:do_shadow_Store(LE)");
}
vdata =3D IRExpr_Const( c );
|