|
From: <sv...@va...> - 2006-01-25 21:30:09
|
Author: sewardj
Date: 2006-01-25 21:29:48 +0000 (Wed, 25 Jan 2006)
New Revision: 1550
Log:
Change the way the ppc backend does ppc32/64 float-integer
conversions. fctiw/fctid/fcfid/stfiwx are now represented explicitly
and are generated by the instruction selector. This removes the need
for hdefs.c to know anything about scratch areas on the stack and
scratch FP registers.
Modified:
trunk/priv/host-ppc/hdefs.c
trunk/priv/host-ppc/hdefs.h
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.c 2006-01-25 03:26:27 UTC (rev 1549)
+++ trunk/priv/host-ppc/hdefs.c 2006-01-25 21:29:48 UTC (rev 1550)
@@ -910,34 +910,32 @@
vassert(sz =3D=3D 4 || sz =3D=3D 8);
return i;
}
-PPCInstr* PPCInstr_FpF64toF32 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpF64toF32;
- i->Pin.FpF64toF32.dst =3D dst;
- i->Pin.FpF64toF32.src =3D src;
+PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data )
+{
+ PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag =3D Pin_FpSTFIW;
+ i->Pin.FpSTFIW.addr =3D addr;
+ i->Pin.FpSTFIW.data =3D data;
return i;
}
-PPCInstr* PPCInstr_FpF64toI32 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpF64toI32;
- i->Pin.FpF64toI32.dst =3D dst;
- i->Pin.FpF64toI32.src =3D src;
+PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ) {
+ PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag =3D Pin_FpRSP;
+ i->Pin.FpRSP.dst =3D dst;
+ i->Pin.FpRSP.src =3D src;
return i;
}
-PPCInstr* PPCInstr_FpF64toI64 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpF64toI64;
- i->Pin.FpF64toI64.dst =3D dst;
- i->Pin.FpF64toI64.src =3D src;
+PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32,=20
+ HReg dst, HReg src ) {
+ PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag =3D Pin_FpCftI;
+ i->Pin.FpCftI.fromI =3D fromI;
+ i->Pin.FpCftI.int32 =3D int32;
+ i->Pin.FpCftI.dst =3D dst;
+ i->Pin.FpCftI.src =3D src;
+ vassert(!(int32 && fromI)); /* no such insn ("fcfiw"). */
return i;
}
-PPCInstr* PPCInstr_FpI64toF64 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpI64toF64;
- i->Pin.FpI64toF64.dst =3D dst;
- i->Pin.FpI64toF64.src =3D src;
- return i;
-}
PPCInstr* PPCInstr_FpCMov ( PPCCondCode cond, HReg dst, HReg src ) {
PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
i->tag =3D Pin_FpCMov;
@@ -1417,37 +1415,35 @@
}
return;
}
- case Pin_FpF64toF32:
+ case Pin_FpSTFIW:
+ vex_printf("stfiwz ");
+ ppHRegPPC(i->Pin.FpSTFIW.data);
+ vex_printf(",0(");
+ ppHRegPPC(i->Pin.FpSTFIW.addr);
+ vex_printf(")");
+ return;
+ case Pin_FpRSP:
vex_printf("frsp ");
- ppHRegPPC(i->Pin.FpF64toF32.dst);
+ ppHRegPPC(i->Pin.FpRSP.dst);
vex_printf(",");
- ppHRegPPC(i->Pin.FpF64toF32.src);
+ ppHRegPPC(i->Pin.FpRSP.src);
return;
- case Pin_FpF64toI32:
- vex_printf("fctiw %%fr7,");
- ppHRegPPC(i->Pin.FpF64toI32.src);
- vex_printf("; stfiwx %%fr7,%%r0,%%r1");
- vex_printf("; lwzx ");
- ppHRegPPC(i->Pin.FpF64toI32.dst);
- vex_printf(",%%r0,%%r1");
+ case Pin_FpCftI: {
+ HChar* str =3D "fc???";
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
False)
+ str =3D "fctid";
+ else
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
True)
+ str =3D "fctiw";
+ else
+ if (i->Pin.FpCftI.fromI =3D=3D True && i->Pin.FpCftI.int32 =3D=3D =
False)
+ str =3D "fcfid";
+ vex_printf("%s ", str);
+ ppHRegPPC(i->Pin.FpCftI.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.FpCftI.src);
return;
- case Pin_FpF64toI64:
- vex_printf("fctid %%fr7,");
- ppHRegPPC(i->Pin.FpF64toI64.src);
- vex_printf("; stfdx %%fr7,%%r0,%%r1");
- vex_printf("; ldx ");
- ppHRegPPC(i->Pin.FpF64toI64.dst);
- vex_printf(",%%r0,%%r1");
- return;
- case Pin_FpI64toF64:
- vex_printf("stdx ");
- ppHRegPPC(i->Pin.FpI64toF64.src);
- vex_printf(",%%r0,%%r1");
- vex_printf("; lfdx %%fr7,%%r0,%%r1");
- vex_printf("; fcfid ");
- ppHRegPPC(i->Pin.FpI64toF64.dst);
- vex_printf(",%%r7");
- return;
+ }
case Pin_FpCMov:
vex_printf("fpcmov (%s) ", showPPCCondCode(i->Pin.FpCMov.cond));
ppHRegPPC(i->Pin.FpCMov.dst);
@@ -1778,25 +1774,18 @@
i->Pin.FpLdSt.reg);
addRegUsage_PPCAMode(u, i->Pin.FpLdSt.addr);
return;
- case Pin_FpF64toF32:
- addHRegUse(u, HRmWrite, i->Pin.FpF64toF32.dst);
- addHRegUse(u, HRmRead, i->Pin.FpF64toF32.src);
+ case Pin_FpSTFIW:
+ addHRegUse(u, HRmRead, i->Pin.FpSTFIW.addr);
+ addHRegUse(u, HRmRead, i->Pin.FpSTFIW.data);
return;
- case Pin_FpF64toI32:
- addHRegUse(u, HRmWrite, i->Pin.FpF64toI32.dst);
- addHRegUse(u, HRmWrite, hregPPC_FPR7());
- addHRegUse(u, HRmRead, i->Pin.FpF64toI32.src);
+ case Pin_FpRSP:
+ addHRegUse(u, HRmWrite, i->Pin.FpRSP.dst);
+ addHRegUse(u, HRmRead, i->Pin.FpRSP.src);
return;
- case Pin_FpF64toI64:
- addHRegUse(u, HRmWrite, i->Pin.FpF64toI64.dst);
- addHRegUse(u, HRmWrite, hregPPC_FPR7());
- addHRegUse(u, HRmRead, i->Pin.FpF64toI64.src);
+ case Pin_FpCftI:
+ addHRegUse(u, HRmWrite, i->Pin.FpCftI.dst);
+ addHRegUse(u, HRmRead, i->Pin.FpCftI.src);
return;
- case Pin_FpI64toF64:
- addHRegUse(u, HRmWrite, i->Pin.FpI64toF64.dst);
- addHRegUse(u, HRmWrite, hregPPC_FPR7());
- addHRegUse(u, HRmRead, i->Pin.FpI64toF64.src);
- return;
case Pin_FpCMov:
addHRegUse(u, HRmModify, i->Pin.FpCMov.dst);
addHRegUse(u, HRmRead, i->Pin.FpCMov.src);
@@ -1983,22 +1972,18 @@
mapReg(m, &i->Pin.FpLdSt.reg);
mapRegs_PPCAMode(m, i->Pin.FpLdSt.addr);
return;
- case Pin_FpF64toF32:
- mapReg(m, &i->Pin.FpF64toF32.dst);
- mapReg(m, &i->Pin.FpF64toF32.src);
+ case Pin_FpSTFIW:
+ mapReg(m, &i->Pin.FpSTFIW.addr);
+ mapReg(m, &i->Pin.FpSTFIW.data);
return;
- case Pin_FpF64toI32:
- mapReg(m, &i->Pin.FpF64toI32.dst);
- mapReg(m, &i->Pin.FpF64toI32.src);
+ case Pin_FpRSP:
+ mapReg(m, &i->Pin.FpRSP.dst);
+ mapReg(m, &i->Pin.FpRSP.src);
return;
- case Pin_FpF64toI64:
- mapReg(m, &i->Pin.FpF64toI64.dst);
- mapReg(m, &i->Pin.FpF64toI64.src);
+ case Pin_FpCftI:
+ mapReg(m, &i->Pin.FpCftI.dst);
+ mapReg(m, &i->Pin.FpCftI.src);
return;
- case Pin_FpI64toF64:
- mapReg(m, &i->Pin.FpI64toF64.dst);
- mapReg(m, &i->Pin.FpI64toF64.src);
- return;
case Pin_FpCMov:
mapReg(m, &i->Pin.FpCMov.dst);
mapReg(m, &i->Pin.FpCMov.src);
@@ -3205,73 +3190,93 @@
goto done;
}
=20
- case Pin_FpF64toF32: {
- UInt fr_dst =3D fregNo(i->Pin.FpF64toF32.dst);
- UInt fr_src =3D fregNo(i->Pin.FpF64toF32.src);
- // frsp, PPC32 p423
- p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0);
+ case Pin_FpSTFIW: {
+ UInt ir_addr =3D iregNo(i->Pin.FpSTFIW.addr, mode64);
+ UInt fr_data =3D fregNo(i->Pin.FpSTFIW.data);
+ // stfiwx (store fp64[lo32] as int32), PPC32 p517
+ // Use rA=3D=3D0, so that EA =3D=3D rB =3D=3D ir_addr
+ p =3D mkFormX(p, 31, fr_data, 0/*rA=3D0*/, ir_addr, 983, 0);
goto done;
}
=20
- case Pin_FpF64toI32: {
- UInt r_dst =3D iregNo(i->Pin.FpF64toI32.dst, mode64);
- UInt fr_src =3D fregNo(i->Pin.FpF64toI32.src);
- UChar fr_tmp =3D 7; // Temp freg
- PPCAMode* am_addr;
-
- // fctiw (conv f64 to i32), PPC32 p404
- p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 14, 0);
-
- // No RI form of stfiwx, so need PPCAMode_RR:
- am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
- hregPPC_GPR0(mode64) );
-
- // stfiwx (store fp64[lo32] as int32), PPC32 p517
- p =3D doAMode_RR(p, 31, 983, fr_tmp, am_addr, mode64);
-
- // lwzx (load int32), PPC32 p463
- p =3D doAMode_RR(p, 31, 23, r_dst, am_addr, mode64);
+ case Pin_FpRSP: {
+ UInt fr_dst =3D fregNo(i->Pin.FpRSP.dst);
+ UInt fr_src =3D fregNo(i->Pin.FpRSP.src);
+ // frsp, PPC32 p423
+ p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0);
goto done;
}
=20
- case Pin_FpF64toI64: {
- UInt r_dst =3D iregNo(i->Pin.FpF64toI64.dst, mode64);
- UInt fr_src =3D fregNo(i->Pin.FpF64toI64.src);
- UChar fr_tmp =3D 7; // Temp freg
- PPCAMode* am_addr;
-
- // fctid (conv f64 to i64), PPC64 p437
- p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 814, 0);
-
- am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
- hregPPC_GPR0(mode64) );
-
- // stfdx (store fp64), PPC64 p589
- p =3D doAMode_RR(p, 31, 727, fr_tmp, am_addr, mode64);
-
- // ldx (load int64), PPC64 p476
- p =3D doAMode_RR(p, 31, 21, r_dst, am_addr, mode64);
- goto done;
+ case Pin_FpCftI: {
+ UInt fr_dst =3D fregNo(i->Pin.FpCftI.dst);
+ UInt fr_src =3D fregNo(i->Pin.FpCftI.src);
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
True) {
+ // fctiw (conv f64 to i32), PPC32 p404
+ p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 14, 0);
+ goto done;
+ }
+ goto bad;
}
=20
- case Pin_FpI64toF64: {
- UInt r_src =3D iregNo(i->Pin.FpI64toF64.src, mode64);
- UInt fr_dst =3D fregNo(i->Pin.FpI64toF64.dst);
- UChar fr_tmp =3D 7; // Temp freg
- PPCAMode* am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
- hregPPC_GPR0(mode64) );
+// case Pin_FpF64toI32: {
+// UInt r_dst =3D iregNo(i->Pin.FpF64toI32.dst, mode64);
+// UInt fr_src =3D fregNo(i->Pin.FpF64toI32.src);
+// UChar fr_tmp =3D 7; // Temp freg
+// PPCAMode* am_addr;
+//
+// // fctiw (conv f64 to i32), PPC32 p404
+// p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 14, 0);
+//
+// // No RI form of stfiwx, so need PPCAMode_RR:
+// am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
+// hregPPC_GPR0(mode64) );
+//
+// // stfiwx (store fp64[lo32] as int32), PPC32 p517
+// p =3D doAMode_RR(p, 31, 983, fr_tmp, am_addr, mode64);
+//
+// // lwzx (load int32), PPC32 p463
+// p =3D doAMode_RR(p, 31, 23, r_dst, am_addr, mode64);
+// goto done;
+// }
+//
+// case Pin_FpF64toI64: {
+// UInt r_dst =3D iregNo(i->Pin.FpF64toI64.dst, mode64);
+// UInt fr_src =3D fregNo(i->Pin.FpF64toI64.src);
+// UChar fr_tmp =3D 7; // Temp freg
+// PPCAMode* am_addr;
+//
+// // fctid (conv f64 to i64), PPC64 p437
+// p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 814, 0);
+//
+// am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
+// hregPPC_GPR0(mode64) );
+//
+// // stfdx (store fp64), PPC64 p589
+// p =3D doAMode_RR(p, 31, 727, fr_tmp, am_addr, mode64);
+//
+// // ldx (load int64), PPC64 p476
+// p =3D doAMode_RR(p, 31, 21, r_dst, am_addr, mode64);
+// goto done;
+// }
+//
+// case Pin_FpI64toF64: {
+// UInt r_src =3D iregNo(i->Pin.FpI64toF64.src, mode64);
+// UInt fr_dst =3D fregNo(i->Pin.FpI64toF64.dst);
+// UChar fr_tmp =3D 7; // Temp freg
+// PPCAMode* am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
+// hregPPC_GPR0(mode64) );
+//
+// // stdx r_src,r0,r1
+// p =3D doAMode_RR(p, 31, 149, r_src, am_addr, mode64);
+//
+// // lfdx fr7,r0,r1
+// p =3D doAMode_RR(p, 31, 599, fr_tmp, am_addr, mode64);
+//
+// // fcfid (conv i64 to f64), PPC64 p434
+// p =3D mkFormX(p, 63, fr_dst, 0, fr_tmp, 846, 0);
+// goto done;
+// }
=20
- // stdx r_src,r0,r1
- p =3D doAMode_RR(p, 31, 149, r_src, am_addr, mode64);
-
- // lfdx fr7,r0,r1
- p =3D doAMode_RR(p, 31, 599, fr_tmp, am_addr, mode64);
-
- // fcfid (conv i64 to f64), PPC64 p434
- p =3D mkFormX(p, 63, fr_dst, 0, fr_tmp, 846, 0);
- goto done;
- }
-
case Pin_FpCMov: {
UInt fr_dst =3D fregNo(i->Pin.FpCMov.dst);
UInt fr_src =3D fregNo(i->Pin.FpCMov.src);
Modified: trunk/priv/host-ppc/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.h 2006-01-25 03:26:27 UTC (rev 1549)
+++ trunk/priv/host-ppc/hdefs.h 2006-01-25 21:29:48 UTC (rev 1550)
@@ -207,8 +207,8 @@
=20
typedef
enum {
- Pam_IR, /* Immediate (signed 16-bit) + Reg */
- Pam_RR /* Reg1 + Reg2 */
+ Pam_IR=3D1, /* Immediate (signed 16-bit) + Reg */
+ Pam_RR=3D2 /* Reg1 + Reg2 */
}
PPCAModeTag;
=20
@@ -240,8 +240,8 @@
/* ("RH" =3D=3D "Register or Halfword immediate") */
typedef=20
enum {
- Prh_Imm=3D1,
- Prh_Reg=3D2
+ Prh_Imm=3D3,
+ Prh_Reg=3D4
}
PPCRHTag;
=20
@@ -271,8 +271,8 @@
=20
typedef
enum {
- Pri_Imm=3D3,
- Pri_Reg=3D4
+ Pri_Imm=3D5,
+ Pri_Reg=3D6
}=20
PPCRITag;
=20
@@ -297,8 +297,8 @@
/* ("VI" =3D=3D "Vector Register or Immediate") */
typedef
enum {
- Pvi_Imm=3D5,
- Pvi_Reg=3D6
+ Pvi_Imm=3D7,
+ Pvi_Reg=3D8
}=20
PPCVI5sTag;
=20
@@ -459,16 +459,15 @@
Pin_FpUnary, /* FP unary op */
Pin_FpBinary, /* FP binary op */
Pin_FpLdSt, /* FP load/store */
- Pin_FpF64toF32, /* FP round IEEE754 double to IEEE754 single */
- Pin_FpF64toI32, /* FP round IEEE754 double to 32-bit integer */
- Pin_FpF64toI64, /* FP round IEEE754 double to 64-bit integer */
- Pin_FpI64toF64, /* FP round IEEE754 64-bit integer to double */
+ Pin_FpSTFIW, /* stfiwx */
+ Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */
+ Pin_FpCftI, /* fcfid/fctid/fctiw */
Pin_FpCMov, /* FP floating point conditional move */
Pin_FpLdFPSCR, /* mtfsf */
Pin_FpCmp, /* FP compare, generating value into int reg */
+
Pin_RdWrLR, /* Read/Write Link Register */
=20
-// Pin_AvConst, /* Generate restricted AV literal */
Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
Pin_AvUnary, /* AV unary general reg=3D>reg */
=20
@@ -636,32 +635,25 @@
HReg reg;
PPCAMode* addr;
} FpLdSt;
- /* By observing the current FPU rounding mode, round src->dst,
- re-interpreting dst to an IEEE754 32-bit (float) type. */
struct {
- HReg src;
- HReg dst;
- } FpF64toF32;
- /* By observing the current FPU rounding mode, round src->dst,
- re-interpreting dst to an 32-bit integer type. */
+ HReg addr; /* int reg */
+ HReg data; /* float reg */
+ } FpSTFIW;
+ /* Round 64-bit FP value to 32-bit FP value in an FP reg. */
struct {
HReg src;
HReg dst;
- } FpF64toI32;
- /* Ditto to 64-bit integer type. */
+ } FpRSP;
+ /* fcfid/fctid/fctiw. Note there's no fcfiw so fromI=3D=3DTrue
+ && int32=3D=3DTrue is not allowed. */
struct {
+ Bool fromI; /* False=3D=3DF->I, True=3D=3DI->F */
+ Bool int32; /* True=3D=3D I is 32, False=3D=3DI is 64 */
HReg src;
HReg dst;
- } FpF64toI64;
- /* By observing the current FPU rounding mode, reinterpret src
- from a 64bit integer to double type, and round into dst. */
+ } FpCftI;
+ /* FP mov src to dst on the given condition. */
struct {
- HReg src;
- HReg dst;
- } FpI64toF64;
- /* Mov src to dst on the given condition, which may not
- be the bogus Xcc_ALWAYS. */
- struct {
PPCCondCode cond;
HReg dst;
HReg src;
@@ -793,10 +785,10 @@
extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, =
HReg srcR );
extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCA=
Mode* );
-extern PPCInstr* PPCInstr_FpF64toF32 ( HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpF64toI32 ( HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpF64toI64 ( HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpI64toF64 ( HReg dst, HReg src );
+extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data );
+extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src );
+extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32,=20
+ HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src )=
;
extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src );
extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR );
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-25 03:26:27 UTC (rev 1549)
+++ trunk/priv/host-ppc/isel.c 2006-01-25 21:29:48 UTC (rev 1550)
@@ -1299,18 +1299,27 @@
}
=20
if (e->Iex.Binop.op =3D=3D Iop_F64toI32) {
- HReg fr_src =3D iselDblExpr(env, e->Iex.Binop.arg2);
- HReg r_dst =3D newVRegI(env); =20
+ /* This works in both mode64 and mode32. */
+ HReg r1 =3D StackFramePtr(env->mode64);
+ PPCAMode* zero_r1 =3D PPCAMode_IR( 0, r1 );
+ HReg fsrc =3D iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg ftmp =3D newVRegF(env);
+ HReg idst =3D newVRegI(env);
+ vassert(!env->mode64); // wait for 64-bit test case
/* Set host rounding mode */
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
sub_from_sp( env, 16 );
- addInstr(env, PPCInstr_FpF64toI32(r_dst, fr_src));
+ addInstr(env, PPCInstr_FpCftI(False/*F->I*/, True/*int32*/,=20
+ ftmp, fsrc));
+ addInstr(env, PPCInstr_FpSTFIW(r1, ftmp));
+ addInstr(env, PPCInstr_Load(4, True/*signed*/,=20
+ idst, zero_r1, mode64));
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
set_FPU_rounding_default( env );
- return r_dst;
+ return idst;
}
=20
if (e->Iex.Binop.op =3D=3D Iop_F64toI64) {
@@ -1320,7 +1329,8 @@
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
sub_from_sp( env, 16 );
- addInstr(env, PPCInstr_FpF64toI64(r_dst, fr_src));
+vassert(0);
+// addInstr(env, PPCInstr_FpF64toI64(r_dst, fr_src));
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
@@ -2638,7 +2648,7 @@
HReg r_dst =3D newVRegF(env);
HReg r_src =3D iselDblExpr(env, e->Iex.Binop.arg2);
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
- addInstr(env, PPCInstr_FpF64toF32(r_dst, r_src));
+ addInstr(env, PPCInstr_FpRSP(r_dst, r_src));
set_FPU_rounding_default( env );
return r_dst;
}
@@ -2780,7 +2790,8 @@
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
sub_from_sp( env, 16 );
- addInstr(env, PPCInstr_FpI64toF64(fr_dst, r_src));
+vassert(0);
+// addInstr(env, PPCInstr_FpI64toF64(fr_dst, r_src));
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
|