|
From: <sv...@va...> - 2006-01-25 03:01:49
|
Author: sewardj
Date: 2006-01-25 03:01:09 +0000 (Wed, 25 Jan 2006)
New Revision: 1548
Log:
Tidy up the ppc instruction selector a bit. This is almost all cosmetic:
- clarify which functions are to be used both in 64-bit and 32-bit mode,
and which are for one or other modes only. Rename accordingly.
- iselWordExpr_AMode: was not generating nice amodes in 64-bit mode.
Fixed.
Modified:
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-24 19:39:02 UTC (rev 1547)
+++ trunk/priv/host-ppc/isel.c 2006-01-25 03:01:09 UTC (rev 1548)
@@ -220,8 +220,8 @@
return env->vregmap[tmp];
}
=20
-static void lookupIRTemp64 ( HReg* vrHI, HReg* vrLO,
- ISelEnv* env, IRTemp tmp )
+static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO,
+ ISelEnv* env, IRTemp tmp )
{
vassert(!env->mode64);
vassert(tmp >=3D 0);
@@ -231,17 +231,6 @@
*vrHI =3D env->vregmapHI[tmp];
}
=20
-static void lookupIRTemp128 ( HReg* vrHI, HReg* vrLO,
- ISelEnv* env, IRTemp tmp )
-{
- vassert(env->mode64);
- vassert(tmp >=3D 0);
- vassert(tmp < env->n_vregmap);
- vassert(env->vregmapHI[tmp] !=3D INVALID_HREG);
- *vrLO =3D env->vregmap[tmp];
- *vrHI =3D env->vregmapHI[tmp];
-}
-
static void addInstr ( ISelEnv* env, PPCInstr* instr )
{
addHInstr(env->code, instr);
@@ -283,48 +272,60 @@
For each XXX, iselXXX calls its iselXXX_wrk counterpart, then
checks that all returned registers are virtual. You should not
call the _wrk version directly.
+
+ 'Word' refers to the size of the native machine word, that is,
+ 32-bit int in 32-bit mode and 64-bit int in 64-bit mode. '2Word'
+ therefore refers to a double-width (64/128-bit) quantity in two
+ integer registers.
*/
-/* Compute an I8/I16/I32 into a GPR. */
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
+/* 32-bit mode: compute an I8/I16/I32 into a GPR.
+ 64-bit mode: compute an I8/I16/I32/I64 into a GPR. */
+static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e );
+static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I8/I16/I32 into a RH (reg-or-halfword-immediate). It's
- important to specify whether the immediate is to be regarded as
- signed or not. If yes, this will never return -32768 as an
+/* 32-bit mode: Compute an I8/I16/I32 into a RH
+ (reg-or-halfword-immediate).
+ 64-bit mode: Compute an I8/I16/I32/I64 into a RH
+ (reg-or-halfword-immediate).
+ It's important to specify whether the immediate is to be regarded
+ as signed or not. If yes, this will never return -32768 as an
immediate; this guaranteed that all signed immediates that are
- return can have their sign inverted if need be. */
-static PPCRH* iselIntExpr_RH_wrk ( ISelEnv* env,=20
- Bool syned, IRExpr* e );
-static PPCRH* iselIntExpr_RH ( ISelEnv* env,=20
- Bool syned, IRExpr* e );
+ return can have their sign inverted if need be.=20
+*/
+static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env,=20
+ Bool syned, IRExpr* e );
+static PPCRH* iselWordExpr_RH ( ISelEnv* env,=20
+ Bool syned, IRExpr* e );
=20
-/* Compute an I32 into a RI (reg or 32-bit immediate). */
-static PPCRI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
-static PPCRI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e );
+/* 32-bit mode: compute an I32 into a RI (reg or 32-bit immediate).
+ 64-bit mode: compute an I64 into a RI (reg or 64-bit immediate). */
+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
+static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter
- being an immediate in the range 1 .. 31 inclusive. Used for doing
- shift amounts. */
-static PPCRH* iselIntExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e );
-static PPCRH* iselIntExpr_RH5u ( ISelEnv* env, IRExpr* e );
+/* In 32 bit mode ONLY, compute an I8 into a
+ reg-or-5-bit-unsigned-immediate, the latter being an immediate in
+ the range 1 .. 31 inclusive. Used for doing shift amounts. */
+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e );
+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter
- being an immediate in the range 1 .. 63 inclusive. Used for doing
- shift amounts. */
-static PPCRH* iselIntExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e );
-static PPCRH* iselIntExpr_RH6u ( ISelEnv* env, IRExpr* e );
+/* In 64-bit mode ONLY, compute an I8 into a Compute an I8 into a
+ reg-or-6-bit-unsigned-immediate, the latter being an immediate in
+ the range 1 .. 63 inclusive. Used for doing shift amounts. */
+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e );
+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I32 into an AMode. */
-static PPCAMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
-static PPCAMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e );
+/* 32-bit mode: compute an I32 into an AMode.
+ 64-bit mode: compute an I64 into an AMode. */
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I64 into a GPR pair. */
+/* 32-bit mode ONLY: compute an I64 into a GPR pair. */
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,=20
ISelEnv* env, IRExpr* e );
static void iselInt64Expr ( HReg* rHi, HReg* rLo,=20
ISelEnv* env, IRExpr* e );
=20
-/* Compute an I128 into a GPR64 pair. */
+/* 64-bit mode ONLY: compute an I128 into a GPR64 pair. */
static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,=20
ISelEnv* env, IRExpr* e );
static void iselInt128Expr ( HReg* rHi, HReg* rLo,=20
@@ -619,7 +620,7 @@
argiregs |=3D (1 << (argreg+3));
addInstr(env,
mk_iMOVds_RR( argregs[argreg],
- iselIntExpr_R(env, args[i]) ));
+ iselWordExpr_R(env, args[i]) ));
} else { // Ity_I64
HReg rHi, rLo;
if (argreg%2 =3D=3D 1) // ppc32 abi spec for passing LONG=
_LONG
@@ -634,7 +635,7 @@
} else { // mode64
argiregs |=3D (1 << (argreg+3));
addInstr(env, mk_iMOVds_RR( argregs[argreg],
- iselIntExpr_R(env, args[i]) ));
+ iselWordExpr_R(env, args[i]) ));
}
argreg++;
}
@@ -662,7 +663,7 @@
typeOfIRExpr(env->type_env, args[i]) =3D=3D Ity_I64);
if (!mode64) {
if (typeOfIRExpr(env->type_env, args[i]) =3D=3D Ity_I32) {=20
- tmpregs[argreg] =3D iselIntExpr_R(env, args[i]);
+ tmpregs[argreg] =3D iselWordExpr_R(env, args[i]);
} else { // Ity_I64
HReg rHi, rLo;
if (argreg%2 =3D=3D 1) // ppc32 abi spec for passing LONG=
_LONG
@@ -673,7 +674,7 @@
tmpregs[argreg] =3D rLo;
}
} else { // mode64
- tmpregs[argreg] =3D iselIntExpr_R(env, args[i]);
+ tmpregs[argreg] =3D iselWordExpr_R(env, args[i]);
}
argreg++;
}
@@ -751,7 +752,7 @@
addi %tmp, %tmp, base
... Baseblockptr + %tmp ...
*/
- roff =3D iselIntExpr_R(env, off);
+ roff =3D iselWordExpr_R(env, off);
rtmp =3D newVRegI(env);
addInstr(env, PPCInstr_Alu(
Palu_ADD,=20
@@ -847,7 +848,7 @@
*/
=20
// Resolve rounding mode and convert to PPC representation
- r_src =3D roundModeIRtoPPC( env, iselIntExpr_R(env, mode) );
+ r_src =3D roundModeIRtoPPC( env, iselWordExpr_R(env, mode) );
// gpr -> fpr
if (env->mode64) {
fr_src =3D mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
@@ -871,7 +872,7 @@
{
HReg r_src;
HReg dst =3D newVRegV(env);
- PPCRI* ri =3D iselIntExpr_RI(env, e);
+ PPCRI* ri =3D iselWordExpr_RI(env, e);
IRType ty =3D typeOfIRExpr(env->type_env,e);
UInt sz =3D (ty =3D=3D Ity_I8) ? 8 : (ty =3D=3D Ity_I16) ? 16 : 32=
;
vassert(ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32);
@@ -991,9 +992,9 @@
if necessary.
*/
=20
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
+static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e )
{
- HReg r =3D iselIntExpr_R_wrk(env, e);
+ HReg r =3D iselWordExpr_R_wrk(env, e);
/* sanity checks ... */
# if 0
vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
@@ -1005,7 +1006,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
{
Bool mode64 =3D env->mode64;
MatchInfo mi;
@@ -1024,7 +1025,7 @@
/* --------- LOAD --------- */
case Iex_Load: {
HReg r_dst =3D newVRegI(env);
- PPCAMode* am_addr =3D iselIntExpr_AMode( env, e->Iex.Load.addr );
+ PPCAMode* am_addr =3D iselWordExpr_AMode( env, e->Iex.Load.addr );
if (e->Iex.Load.end !=3D Iend_BE)
goto irreducible;
addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),=20
@@ -1057,20 +1058,20 @@
values are on the second operand. */
if (aluOp !=3D Palu_INVALID) {
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
PPCRH* ri_srcR =3D NULL;
/* get right arg into an RH, in the appropriate way */
switch (aluOp) {
case Palu_ADD: case Palu_SUB:
- ri_srcR =3D iselIntExpr_RH(env, True/*signed*/,=20
- e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH(env, True/*signed*/,=20
+ e->Iex.Binop.arg2);
break;
case Palu_AND: case Palu_OR: case Palu_XOR:
- ri_srcR =3D iselIntExpr_RH(env, False/*signed*/,
- e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH(env, False/*signed*/,
+ e->Iex.Binop.arg2);
break;
default:
- vpanic("iselIntExpr_R_wrk-aluOp-arg2");
+ vpanic("iselWordExpr_R_wrk-aluOp-arg2");
}
addInstr(env, PPCInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
return r_dst;
@@ -1090,15 +1091,15 @@
/* we assume any literal values are on the second operand. */
if (shftOp !=3D Pshft_INVALID) {
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
PPCRH* ri_srcR =3D NULL;
/* get right arg into an RH, in the appropriate way */
switch (shftOp) {
case Pshft_SHL: case Pshft_SHR: case Pshft_SAR:
if (!mode64)
- ri_srcR =3D iselIntExpr_RH5u(env, e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH5u(env, e->Iex.Binop.arg2);
else
- ri_srcR =3D iselIntExpr_RH6u(env, e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
break;
default:
vpanic("iselIntExpr_R_wrk-shftOp-arg2");
@@ -1137,8 +1138,8 @@
e->Iex.Binop.op =3D=3D Iop_DivU32) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_DivS32);
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_Div(syned, True/*32bit div*/,
r_dst, r_srcL, r_srcR));
return r_dst;
@@ -1147,8 +1148,8 @@
e->Iex.Binop.op =3D=3D Iop_DivU64) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_DivS64);
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
vassert(mode64);
addInstr(env, PPCInstr_Div(syned, False/*64bit div*/,
r_dst, r_srcL, r_srcR));
@@ -1156,29 +1157,28 @@
}
=20
/* No? Anyone for a mul? */
- if (e->Iex.Binop.op =3D=3D Iop_Mul16 ||
- e->Iex.Binop.op =3D=3D Iop_Mul32 ||
- e->Iex.Binop.op =3D=3D Iop_Mul64) {
+ if (e->Iex.Binop.op =3D=3D Iop_Mul32
+ || e->Iex.Binop.op =3D=3D Iop_Mul64) {
Bool syned =3D False;
Bool sz32 =3D (e->Iex.Binop.op !=3D Iop_Mul64);
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(syned, False/*lo32*/, sz32,
r_dst, r_srcL, r_srcR));
return r_dst;
} =20
=20
/* 32 x 32 -> 64 multiply */
- if (e->Iex.Binop.op =3D=3D Iop_MullU32 ||
- e->Iex.Binop.op =3D=3D Iop_MullS32) {
+ if (mode64
+ && (e->Iex.Binop.op =3D=3D Iop_MullU32
+ || e->Iex.Binop.op =3D=3D Iop_MullS32)) {
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
HReg r_dst =3D newVRegI(env);
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_MullS32);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
- vassert(mode64);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
False/*lo32*/, True/*32bit mul*/,
tLo, r_srcL, r_srcR));
@@ -1193,12 +1193,12 @@
}
=20
/* El-mutanto 3-way compare? */
- if (e->Iex.Binop.op =3D=3D Iop_CmpORD32S ||
- e->Iex.Binop.op =3D=3D Iop_CmpORD32U) {
+ if (e->Iex.Binop.op =3D=3D Iop_CmpORD32S
+ || e->Iex.Binop.op =3D=3D Iop_CmpORD32U) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_CmpORD32S);
HReg dst =3D newVRegI(env);
- HReg srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* srcR =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* srcR =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2)=
;
addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/,
7/*cr*/, srcL, srcR));
addInstr(env, PPCInstr_MfCR(dst));
@@ -1207,12 +1207,12 @@
return dst;
}
=20
- if (e->Iex.Binop.op =3D=3D Iop_CmpORD64S ||
- e->Iex.Binop.op =3D=3D Iop_CmpORD64U) {
+ if (e->Iex.Binop.op =3D=3D Iop_CmpORD64S
+ || e->Iex.Binop.op =3D=3D Iop_CmpORD64U) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_CmpORD64S);
HReg dst =3D newVRegI(env);
- HReg srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* srcR =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* srcR =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2)=
;
vassert(mode64);
addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
7/*cr*/, srcL, srcR));
@@ -1223,8 +1223,8 @@
}
=20
if (e->Iex.Binop.op =3D=3D Iop_32HLto64) {
- HReg r_Hi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_Lo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_Hi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_Lo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
HReg r_dst =3D newVRegI(env);
HReg msk =3D newVRegI(env);
vassert(mode64);
@@ -1341,7 +1341,7 @@
if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) {
IRExpr* expr32 =3D mi.bindee[0];
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, expr32);
+ HReg r_src =3D iselWordExpr_R(env, expr32);
addInstr(env, PPCInstr_Alu(Palu_AND, r_dst,
r_src, PPCRH_Imm(False,1)));
return r_dst;
@@ -1355,7 +1355,7 @@
IRExpr_Load(Iend_BE,Ity_I16,bind(0))) );
if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) {
HReg r_dst =3D newVRegI(env);
- PPCAMode* amode =3D iselIntExpr_AMode( env, mi.bindee[0] );
+ PPCAMode* amode =3D iselWordExpr_AMode( env, mi.bindee[0] );
addInstr(env, PPCInstr_Load(2,False,r_dst,amode, mode64));
return r_dst;
}
@@ -1368,7 +1368,7 @@
case Iop_16Uto32:
case Iop_16Uto64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort mask =3D toUShort(op_unop=3D=3DIop_16Uto64 ? 0xFFFF :
op_unop=3D=3DIop_16Uto32 ? 0xFFFF : 0xF=
F);
addInstr(env, PPCInstr_Alu(Palu_AND,r_dst,r_src,
@@ -1377,7 +1377,7 @@
}
case Iop_32Uto64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
vassert(mode64);
addInstr(env,
PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
@@ -1391,7 +1391,7 @@
case Iop_8Sto32:
case Iop_16Sto32: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort amt =3D toUShort(op_unop=3D=3DIop_16Sto32 ? 16 : 24);
addInstr(env,
PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
@@ -1405,7 +1405,7 @@
case Iop_16Sto64:
case Iop_32Sto64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort amt =3D toUShort(op_unop=3D=3DIop_8Sto64 ? 56 :
op_unop=3D=3DIop_16Sto64 ? 48 : 32);
vassert(mode64);
@@ -1422,7 +1422,7 @@
case Iop_Not32:
case Iop_Not64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Unary(Pun_NOT,r_dst,r_src));
return r_dst;
}
@@ -1433,7 +1433,7 @@
return rHi; /* and abandon rLo .. poor wee thing :-) */
} else {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env,
PPCInstr_Shft(Pshft_SHR, False/*64bit shift*/,
r_dst, r_src, PPCRH_Imm(False,32)));
@@ -1447,36 +1447,39 @@
return rLo; /* similar stupid comment to the above ... */
} else {
/* This is a no-op. */
- return iselIntExpr_R(env, e->Iex.Unop.arg);
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
}
}
case Iop_64to16: {
if (mode64) { /* This is a no-op. */
- return iselIntExpr_R(env, e->Iex.Unop.arg);
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
}
+ break; /* evidently not used in 32-bit mode */
}
case Iop_16HIto8:
case Iop_32HIto16: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort shift =3D toUShort(op_unop =3D=3D Iop_16HIto8 ? 8 : 16);
addInstr(env,
PPCInstr_Shft(Pshft_SHR, True/*32bit shift*/,
r_dst, r_src, PPCRH_Imm(False,shift)));
return r_dst;
}
- case Iop_128HIto64: {
- HReg rHi, rLo;
- vassert(mode64);
- iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
- return rHi; /* and abandon rLo .. poor wee thing :-) */
- }
- case Iop_128to64: {
- vassert(mode64);
- HReg rHi, rLo;
- iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
- return rLo; /* similar stupid comment to the above ... */
- }
+ case Iop_128HIto64:=20
+ if (mode64) {
+ HReg rHi, rLo;
+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
+ return rHi; /* and abandon rLo .. poor wee thing :-) */
+ }
+ break;
+ case Iop_128to64:
+ if (mode64) {
+ HReg rHi, rLo;
+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
+ return rLo; /* similar stupid comment to the above ... */
+ }
+ break;
case Iop_1Uto32:
case Iop_1Uto8: {
HReg r_dst =3D newVRegI(env);
@@ -1499,24 +1502,28 @@
r_dst, r_dst, PPCRH_Imm(False,31)));
return r_dst;
}
- case Iop_1Sto64: {
- /* could do better than this, but for now ... */
- HReg r_dst =3D newVRegI(env);
- PPCCondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_Set(cond,r_dst));
- addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
- r_dst, r_dst, PPCRH_Imm(False,63)))=
;
- addInstr(env, PPCInstr_Shft(Pshft_SAR, False/*64bit shift*/,
- r_dst, r_dst, PPCRH_Imm(False,63)))=
;
- return r_dst;
- }
+ case Iop_1Sto64:=20
+ if (mode64) {
+ /* could do better than this, but for now ... */
+ HReg r_dst =3D newVRegI(env);
+ PPCCondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_Set(cond,r_dst));
+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
+ r_dst, r_dst, PPCRH_Imm(False,63=
)));
+ addInstr(env, PPCInstr_Shft(Pshft_SAR, False/*64bit shift*/,
+ r_dst, r_dst, PPCRH_Imm(False,63=
)));
+ return r_dst;
+ }
+ break;
case Iop_Clz32:
case Iop_Clz64: {
PPCUnaryOp op_clz =3D (op_unop =3D=3D Iop_Clz32) ? Pun_CLZ32 :
Pun_CLZ64;
+ if (op_unop =3D=3D Iop_Clz64 && !mode64)
+ goto irreducible;
/* Count leading zeroes. */
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
return r_dst;
}
@@ -1525,7 +1532,9 @@
case Iop_Neg32:
case Iop_Neg64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ if (op_unop =3D=3D Iop_Neg64 && !mode64)
+ goto irreducible;
addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src));
return r_dst;
}
@@ -1553,61 +1562,65 @@
}
=20
case Iop_V128to64:
- case Iop_V128HIto64: {
- HReg r_aligned16;
- HReg dst =3D newVRegI(env);
- HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
- PPCAMode *am_off0, *am_off8;
- vassert(mode64);
- sub_from_sp( env, 32 ); // Move SP down 32 bytes
+ case Iop_V128HIto64:=20
+ if (mode64) {
+ HReg r_aligned16;
+ HReg dst =3D newVRegI(env);
+ HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
+ PPCAMode *am_off0, *am_off8;
+ sub_from_sp( env, 32 ); // Move SP down 32 bytes
=20
- // get a quadword aligned address within our stack space
- r_aligned16 =3D get_sp_aligned16( env );
- am_off0 =3D PPCAMode_IR( 0, r_aligned16 );
- am_off8 =3D PPCAMode_IR( 8 ,r_aligned16 );
+ // get a quadword aligned address within our stack space
+ r_aligned16 =3D get_sp_aligned16( env );
+ am_off0 =3D PPCAMode_IR( 0, r_aligned16 );
+ am_off8 =3D PPCAMode_IR( 8 ,r_aligned16 );
=20
- // store vec, load low word (+8) or high (+0) to dst
- addInstr(env,
- PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 ));
- addInstr(env,
- PPCInstr_Load( 8, False, dst,=20
- op_unop =3D=3D Iop_V128HIto64 ? am_o=
ff0 : am_off8,=20
- mode64 ));
+ // store vec, load low word (+8) or high (+0) to dst
+ addInstr(env,
+ PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 )=
);
+ addInstr(env,
+ PPCInstr_Load(=20
+ 8, False, dst,=20
+ op_unop =3D=3D Iop_V128HIto64 ? am_off0 : am_off=
8,=20
+ mode64 ));
=20
- add_to_sp( env, 32 ); // Reset SP
- return dst;
- }
-
+ add_to_sp( env, 32 ); // Reset SP
+ return dst;
+ }
+ break;
case Iop_16to8:
case Iop_32to8:
case Iop_32to16:
case Iop_64to8:
/* These are no-ops. */
- return iselIntExpr_R(env, e->Iex.Unop.arg);
+ if (op_unop =3D=3D Iop_Neg64 && !mode64)
+ goto irreducible;
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
=20
/* ReinterpF64asI64(e) */
/* Given an IEEE754 double, produce an I64 with the same bit
pattern. */
- case Iop_ReinterpF64asI64: {
- PPCAMode *am_addr;
- HReg fr_src =3D iselDblExpr(env, e->Iex.Unop.arg);
- HReg r_dst =3D newVRegI(env);
- vassert(mode64);
+ case Iop_ReinterpF64asI64:=20
+ if (mode64) {
+ PPCAMode *am_addr;
+ HReg fr_src =3D iselDblExpr(env, e->Iex.Unop.arg);
+ HReg r_dst =3D newVRegI(env);
=20
- sub_from_sp( env, 16 ); // Move SP down 16 bytes
- am_addr =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
+ sub_from_sp( env, 16 ); // Move SP down 16 bytes
+ am_addr =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
=20
- // store as F64
- addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
- fr_src, am_addr ));
- // load as Ity_I64
- addInstr(env, PPCInstr_Load( 8, False,
- r_dst, am_addr, mode64 ));
+ // store as F64
+ addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
+ fr_src, am_addr ));
+ // load as Ity_I64
+ addInstr(env, PPCInstr_Load( 8, False,
+ r_dst, am_addr, mode64 ));
=20
- add_to_sp( env, 16 ); // Reset SP
- return r_dst;
- }
- =20
+ add_to_sp( env, 16 ); // Reset SP
+ return r_dst;
+ }
+ break;
+
default:=20
break;
}
@@ -1666,12 +1679,12 @@
HReg r_dst =3D newVRegI(env);
IRConst* con =3D e->Iex.Const.con;
switch (con->tag) {
- case Ico_U64: vassert(mode64);
- l =3D (Long) con->Ico.U64; break;
- case Ico_U32: l =3D (Long)(Int) con->Ico.U32; break;
- case Ico_U16: l =3D (Long)(Int)(Short)con->Ico.U16; break;
- case Ico_U8: l =3D (Long)(Int)(Char )con->Ico.U8; break;
- default: vpanic("iselIntExpr_R.const(ppc)");
+ case Ico_U64: if (!mode64) goto irreducible;
+ l =3D (Long) con->Ico.U64; break;
+ case Ico_U32: l =3D (Long)(Int) con->Ico.U32; break;
+ case Ico_U16: l =3D (Long)(Int)(Short)con->Ico.U16; break;
+ case Ico_U8: l =3D (Long)(Int)(Char )con->Ico.U8; break;
+ default: vpanic("iselIntExpr_R.const(ppc)");
}
addInstr(env, PPCInstr_LI(r_dst, (ULong)l, mode64));
return r_dst;
@@ -1683,9 +1696,9 @@
ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64)) &&
typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) =3D=3D Ity_I8) {
PPCCondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
- HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
- HReg rX =3D iselIntExpr_R(env, e->Iex.Mux0X.exprX);
- PPCRI* r0 =3D iselIntExpr_RI(env, e->Iex.Mux0X.expr0);
+ HReg r_cond =3D iselWordExpr_R(env, e->Iex.Mux0X.cond);
+ HReg rX =3D iselWordExpr_R(env, e->Iex.Mux0X.exprX);
+ PPCRI* r0 =3D iselWordExpr_RI(env, e->Iex.Mux0X.expr0);
HReg r_dst =3D newVRegI(env);
HReg r_tmp =3D newVRegI(env);
addInstr(env, mk_iMOVds_RR(r_dst,rX));
@@ -1719,10 +1732,10 @@
=20
/* Return an AMode which computes the value of the specified
expression, possibly also adding insns to the code list as a
- result. The expression may only be a 32-bit one.
+ result. The expression may only be a word-size one.
*/
=20
-static Bool fits16bits ( UInt u )=20
+static Bool uInt_fits_in_16_bits ( UInt u )=20
{
/* Is u the same as the sign-extend of its lower 16 bits? */
Int i =3D u & 0xFFFF;
@@ -1731,14 +1744,25 @@
return toBool(u =3D=3D (UInt)i);
}
=20
+static Bool uLong_fits_in_16_bits ( ULong u )=20
+{
+ /* Is u the same as the sign-extend of its lower 16 bits? */
+ Long i =3D u & 0xFFFFULL;
+ i <<=3D 48;
+ i >>=3D 48;
+ return toBool(u =3D=3D (ULong)i);
+}
+
static Bool sane_AMode ( ISelEnv* env, PPCAMode* am )
{
Bool mode64 =3D env->mode64;
switch (am->tag) {
case Pam_IR:
+ /* Using uInt_fits_in_16_bits in 64-bit mode seems a bit bogus,
+ somehow, but I think it's OK. */
return toBool( hregClass(am->Pam.IR.base) =3D=3D HRcGPR(mode64) &&=
=20
hregIsVirtual(am->Pam.IR.base) &&=20
- fits16bits(am->Pam.IR.index) );
+ uInt_fits_in_16_bits(am->Pam.IR.index) );
case Pam_RR:
return toBool( hregClass(am->Pam.RR.base) =3D=3D HRcGPR(mode64) &&=
=20
hregIsVirtual(am->Pam.RR.base) &&
@@ -1749,57 +1773,84 @@
}
}
=20
-static PPCAMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e )
+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e )
{
- PPCAMode* am =3D iselIntExpr_AMode_wrk(env, e);
+ PPCAMode* am =3D iselWordExpr_AMode_wrk(env, e);
vassert(sane_AMode(env, am));
return am;
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCAMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
- vassert(ty =3D=3D (env->mode64 ? Ity_I64 : Ity_I32));
+
+ if (env->mode64) {
+
+ vassert(ty =3D=3D Ity_I64);
=20
- /* Add32(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
- if (e->tag =3D=3D Iex_Binop=20
- && e->Iex.Binop.op =3D=3D Iop_Add32
- && e->Iex.Binop.arg2->tag =3D=3D Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->tag =3D=3D Ico_U32
- && fits16bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U32)) {
- return PPCAMode_IR( e->Iex.Binop.arg2->Iex.Const.con->Ico.U32,
- iselIntExpr_R(env, e->Iex.Binop.arg1) );
- }
+ /* Add64(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add64
+ && e->Iex.Binop.arg2->tag =3D=3D Iex_Const
+ && e->Iex.Binop.arg2->Iex.Const.con->tag =3D=3D Ico_U64
+ && uLong_fits_in_16_bits(e->Iex.Binop.arg2
+ ->Iex.Const.con->Ico.U64)) {
+ return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.=
U64,
+ iselWordExpr_R(env, e->Iex.Binop.arg1) );
+ }
=20
- /* Add32(expr,expr) */
- if (e->tag =3D=3D Iex_Binop=20
- && e->Iex.Binop.op =3D=3D Iop_Add32) {
- HReg r_base =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_idx =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
- return PPCAMode_RR( r_idx, r_base );
+ /* Add64(expr,expr) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add64) {
+ HReg r_base =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_idx =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
+ return PPCAMode_RR( r_idx, r_base );
+ }
+
+ } else {
+
+ vassert(ty =3D=3D Ity_I32);
+ =20
+ /* Add32(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add32
+ && e->Iex.Binop.arg2->tag =3D=3D Iex_Const
+ && e->Iex.Binop.arg2->Iex.Const.con->tag =3D=3D Ico_U32
+ && uInt_fits_in_16_bits(e->Iex.Binop.arg2
+ ->Iex.Const.con->Ico.U32)) {
+ return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.=
U32,
+ iselWordExpr_R(env, e->Iex.Binop.arg1) );
+ }
+ =20
+ /* Add32(expr,expr) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add32) {
+ HReg r_base =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_idx =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
+ return PPCAMode_RR( r_idx, r_base );
+ }
+
}
=20
/* Doesn't match anything in particular. Generate it into
a register and use that. */
- {
- HReg r1 =3D iselIntExpr_R(env, e);
- return PPCAMode_IR( 0, r1 );
- }
+ return PPCAMode_IR( 0, iselWordExpr_R(env,e) );
}
=20
=20
/* --------------------- RH --------------------- */
=20
-/* Compute an I8/I16/I32 into a RH (reg-or-halfword-immediate). It's
- important to specify whether the immediate is to be regarded as
- signed or not. If yes, this will never return -32768 as an
- immediate; this guaranteed that all signed immediates that are
- return can have their sign inverted if need be. */
+/* Compute an I8/I16/I32 (and I64, in 64-bit mode) into a RH
+ (reg-or-halfword-immediate). It's important to specify whether the
+ immediate is to be regarded as signed or not. If yes, this will
+ never return -32768 as an immediate; this guaranteed that all
+ signed immediates that are return can have their sign inverted if
+ need be. */
=20
-static PPCRH* iselIntExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e )
+static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e )
{
- PPCRH* ri =3D iselIntExpr_RH_wrk(env, syned, e);
+ PPCRH* ri =3D iselWordExpr_RH_wrk(env, syned, e);
/* sanity checks ... */
switch (ri->tag) {
case Prh_Imm:
@@ -1817,7 +1868,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselIntExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e )
+static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e =
)
{
ULong u;
Long l;
@@ -1850,21 +1901,19 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRH_Reg(r);
- }
+ return PPCRH_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
/* --------------------- RIs --------------------- */
=20
/* Calculate an expression into an PPCRI operand. As with
- iselIntExpr_R, the expression can have type 32, 16 or 8 bits. */
+ iselIntExpr_R, the expression can have type 32, 16 or 8 bits, or,
+ in 64-bit mode, 64 bits. */
=20
-static PPCRI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e )
+static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e )
{
- PPCRI* ri =3D iselIntExpr_RI_wrk(env, e);
+ PPCRI* ri =3D iselWordExpr_RI_wrk(env, e);
/* sanity checks ... */
switch (ri->tag) {
case Pri_Imm:
@@ -1879,7 +1928,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
{
Long l;
IRType ty =3D typeOfIRExpr(env->type_env,e);
@@ -1901,10 +1950,7 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRI_Reg(r);
- }
+ return PPCRI_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
@@ -1912,11 +1958,13 @@
=20
/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter
being an immediate in the range 1 .. 31 inclusive. Used for doing
- shift amounts. */
+ shift amounts. Only used in 32-bit mode. */
=20
-static PPCRH* iselIntExpr_RH5u ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e )
{
- PPCRH* ri =3D iselIntExpr_RH5u_wrk(env, e);
+ PPCRH* ri;
+ vassert(!env->mode64);
+ ri =3D iselWordExpr_RH5u_wrk(env, e);
/* sanity checks ... */
switch (ri->tag) {
case Prh_Imm:
@@ -1933,7 +1981,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselIntExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(ty =3D=3D Ity_I8);
@@ -1947,10 +1995,7 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRH_Reg(r);
- }
+ return PPCRH_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
@@ -1958,11 +2003,13 @@
=20
/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter
being an immediate in the range 1 .. 63 inclusive. Used for doing
- shift amounts. */
+ shift amounts. Only used in 64-bit mode. */
=20
-static PPCRH* iselIntExpr_RH6u ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e )
{
- PPCRH* ri =3D iselIntExpr_RH6u_wrk(env, e);
+ PPCRH* ri;=20
+ vassert(env->mode64);
+ ri =3D iselWordExpr_RH6u_wrk(env, e);
/* sanity checks ... */
switch (ri->tag) {
case Prh_Imm:
@@ -1979,7 +2026,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselIntExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(ty =3D=3D Ity_I8);
@@ -1993,10 +2040,7 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRH_Reg(r);
- }
+ return PPCRH_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
@@ -2036,12 +2080,12 @@
return cond;
}
=20
- /* --- patterns rooted at: 32to1 --- */
+ /* --- patterns rooted at: 32to1 or 64to1 --- */
=20
- /* 32to1 */
+ /* 32to1, 64to1 */
if (e->tag =3D=3D Iex_Unop &&
(e->Iex.Unop.op =3D=3D Iop_32to1 || e->Iex.Unop.op =3D=3D Iop_64t=
o1)) {
- HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
HReg tmp =3D newVRegI(env);
/* could do better, probably -- andi. */
addInstr(env, PPCInstr_Alu(Palu_AND, tmp,
@@ -2057,12 +2101,12 @@
/* could do better -- andi. */
if (e->tag =3D=3D Iex_Unop
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ8) {
- HReg r_32 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- HReg r_l =3D newVRegI(env);
- addInstr(env, PPCInstr_Alu(Palu_AND, r_l, r_32,
+ HReg arg =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ HReg tmp =3D newVRegI(env);
+ addInstr(env, PPCInstr_Alu(Palu_AND, tmp, arg,
PPCRH_Imm(False,0xFF)));
addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
- 7/*cr*/, r_l, PPCRH_Imm(False,0)));
+ 7/*cr*/, tmp, PPCRH_Imm(False,0)));
return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
}
=20
@@ -2071,13 +2115,13 @@
/* CmpNEZ32(x) */
if (e->tag =3D=3D Iex_Unop
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ32) {
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r1 =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
7/*cr*/, r1, PPCRH_Imm(False,0)));
return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
}
=20
- /* --- patterns rooted at: Cmp{EQ,NE}{8,16} --- */
+ /* --- patterns rooted at: Cmp*32* --- */
=20
/* Cmp*32*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
@@ -2089,8 +2133,8 @@
|| e->Iex.Binop.op =3D=3D Iop_CmpLE32U)) {
Bool syned =3D (e->Iex.Binop.op =3D=3D Iop_CmpLT32S ||
e->Iex.Binop.op =3D=3D Iop_CmpLE32S);
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg r1 =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* ri2 =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/,
7/*cr*/, r1, ri2));
=20
@@ -2103,6 +2147,30 @@
}
}
=20
+ /* --- patterns rooted at: CmpNEZ64 --- */
+
+ /* CmpNEZ64 */
+ if (e->tag =3D=3D Iex_Unop=20
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
+ if (!env->mode64) {
+ HReg hi, lo;
+ HReg tmp =3D newVRegI(env);
+ iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg );
+ addInstr(env, mk_iMOVds_RR(tmp, lo));
+ addInstr(env, PPCInstr_Alu(Palu_OR, tmp, tmp, PPCRH_Reg(hi)));
+ addInstr(env, PPCInstr_Cmp(False/*sign*/, True/*32bit cmp*/,
+ 7/*cr*/, tmp,PPCRH_Imm(False,0)));
+ return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
+ } else { // mode64
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/,
+ 7/*cr*/, r_src,PPCRH_Imm(False,0)));
+ return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
+ }
+ }
+
+ /* --- patterns rooted at: Cmp*64* --- */
+
/* Cmp*64*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_CmpEQ64
@@ -2113,8 +2181,8 @@
|| e->Iex.Binop.op =3D=3D Iop_CmpLE64U)) {
Bool syned =3D (e->Iex.Binop.op =3D=3D Iop_CmpLT64S ||
e->Iex.Binop.op =3D=3D Iop_CmpLE64S);
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg r1 =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* ri2 =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
vassert(env->mode64);
addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
7/*cr*/, r1, ri2));
@@ -2128,26 +2196,6 @@
}
}
=20
- /* CmpNEZ64 */
- if (e->tag =3D=3D Iex_Unop=20
- && e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
- if (!env->mode64) {
- HReg hi, lo;
- HReg tmp =3D newVRegI(env);
- iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg );
- addInstr(env, mk_iMOVds_RR(tmp, lo));
- addInstr(env, PPCInstr_Alu(Palu_OR, tmp, tmp, PPCRH_Reg(hi)));
- addInstr(env, PPCInstr_Cmp(False/*sign*/, True/*32bit cmp*/,
- 7/*cr*/, tmp,PPCRH_Imm(False,0)));
- return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
- } else { // mode64
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/,
- 7/*cr*/, r_src,PPCRH_Imm(False,0)));
- return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
- }
- }
-
/* var */
if (e->tag =3D=3D Iex_Tmp) {
HReg r_src =3D lookupIRTemp(env, e->Iex.Tmp.tmp);
@@ -2168,13 +2216,14 @@
=20
=20
/*---------------------------------------------------------*/
-/*--- ISEL: Integer expressions (128 bit) ---*/
+/*--- ISEL: Integer expressions (128 bit) ---*/
/*---------------------------------------------------------*/
=20
-/* Compute a 128-bit value into a register pair, which is returned as
- the first two parameters. As with iselIntExpr_R, these may be
- either real or virtual regs; in any case they must not be changed
- by subsequent code emitted by the caller. */
+/* 64-bit mode ONLY: compute a 128-bit value into a register pair,
+ which is returned as the first two parameters. As with
+ iselWordExpr_R, these may be either real or virtual regs; in any
+ case they must not be changed by subsequent code emitted by the
+ caller. */
=20
static void iselInt128Expr ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
@@ -2199,7 +2248,7 @@
=20
/* read 128-bit IRTemp */
if (e->tag =3D=3D Iex_Tmp) {
- lookupIRTemp128( rHi, rLo, env, e->Iex.Tmp.tmp);
+ lookupIRTempPair( rHi, rLo, env, e->Iex.Tmp.tmp);
return;
}
=20
@@ -2212,8 +2261,8 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_MullS64)=
;
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
False/*lo64*/, False/*64bit mul*/,
tLo, r_srcL, r_srcR));
@@ -2227,8 +2276,8 @@
=20
/* 64HLto128(e1,e2) */
case Iop_64HLto128:
- *rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- *rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ *rHi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ *rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
return;
=20
default:=20
@@ -2255,10 +2304,11 @@
/*--- ISEL: Integer expressions (64 bit) ---*/
/*---------------------------------------------------------*/
=20
-/* Compute a 64-bit value into a register pair, which is returned as
- the first two parameters. As with iselIntExpr_R, these may be
- either real or virtual regs; in any case they must not be changed
- by subsequent code emitted by the caller. */
+/* 32-bit mode ONLY: compute a 64-bit value into a register pair,
+ which is returned as the first two parameters. As with
+ iselIntExpr_R, these may be either real or virtual regs; in any
+ case they must not be changed by subsequent code emitted by the
+ caller. */
=20
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
@@ -2278,8 +2328,6 @@
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
{
- Bool mode64 =3D env->mode64;
-// HWord fn =3D 0; /* helper fn for most SIMD64 stuff */
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) =3D=3D Ity_I64);
=20
@@ -2291,8 +2339,8 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
vassert(e->Iex.Const.con->tag =3D=3D Ico_U64);
- addInstr(env, PPCInstr_LI(tHi, wHi, mode64));
- addInstr(env, PPCInstr_LI(tLo, wLo, mode64));
+ addInstr(env, PPCInstr_LI(tHi, wHi, False/*mode32*/));
+ addInstr(env, PPCInstr_LI(tLo, wLo, False/*mode32*/));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2300,19 +2348,19 @@
=20
/* read 64-bit IRTemp */
if (e->tag =3D=3D Iex_Tmp) {
- lookupIRTemp64( rHi, rLo, env, e->Iex.Tmp.tmp);
+ lookupIRTempPair( rHi, rLo, env, e->Iex.Tmp.tmp);
return;
}
=20
/* 64-bit GET */
if (e->tag =3D=3D Iex_Get) {
PPCAMode* am_addr =3D PPCAMode_IR( e->Iex.Get.offset,
- GuestStatePtr(mode64) );
+ GuestStatePtr(False/*mode32*/) );
PPCAMode* am_addr4 =3D advance4(env, am_addr);
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
- addInstr(env, PPCInstr_Load( 4, False, tHi, am_addr, mode64 ));
- addInstr(env, PPCInstr_Load( 4, False, tLo, am_addr4, mode64 ));
+ addInstr(env, PPCInstr_Load( 4, False, tHi, am_addr, False/*mode3=
2*/ ));
+ addInstr(env, PPCInstr_Load( 4, False, tLo, am_addr4, False/*mode3=
2*/ ));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2325,7 +2373,7 @@
HReg tHi =3D newVRegI(env);
=20
PPCCondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
- HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_cond =3D iselWordExpr_R(env, e->Iex.Mux0X.cond);
HReg r_tmp =3D newVRegI(env);
=20
iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.Mux0X.expr0);
@@ -2355,8 +2403,8 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
Bool syned =3D toBool(op_binop =3D=3D Iop_MullS32);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
False/*lo32*/, True/*32bit mul*/=
,
tLo, r_srcL, r_srcR));
@@ -2404,8 +2452,8 @@
=20
/* 32HLto64(e1,e2) */
case Iop_32HLto64:
- *rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- *rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ *rHi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ *rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
return;
=20
default:=20
@@ -2421,7 +2469,7 @@
/* 32Sto64(e) */
case Iop_32Sto64: {
HReg tHi =3D newVRegI(env);
- HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/,
tHi, src, PPCRH_Imm(False,31)));
*rHi =3D tHi;
@@ -2432,8 +2480,8 @@
/* 32Uto64(e) */
case Iop_32Uto64: {
HReg tHi =3D newVRegI(env);
- HReg tLo =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_LI(tHi, 0, mode64));
+ HReg tLo =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_LI(tHi, 0, False/*mode32*/));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2462,9 +2510,9 @@
=20
// load hi,lo words (of hi/lo half of vec) as Ity_I32's
addInstr(env,
- PPCInstr_Load( 4, False, tHi, am_offHI, mode64 ));
+ PPCInstr_Load( 4, False, tHi, am_offHI, False/*mode32*=
/ ));
addInstr(env,
- PPCInstr_Load( 4, False, tLo, am_offLO, mode64 ));
+ PPCInstr_Load( 4, False, tLo, am_offLO, False/*mode32*=
/ ));
=20
add_to_sp( env, 32 ); // Reset SP
*rHi =3D tHi;
@@ -2494,7 +2542,7 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_LI(zero, 0, mode64));
+ addInstr(env, PPCInstr_LI(zero, 0, False/*mode32*/));
addInstr(env, PPCInstr_AddSubC( False/*sub*/, True/*set carry*/=
,
tLo, zero, yLo));
addInstr(env, PPCInstr_AddSubC( False/*sub*/, False/*read carry=
*/,
@@ -2514,8 +2562,8 @@
HReg r_dstHi =3D newVRegI(env);
=20
sub_from_sp( env, 16 ); // Move SP down 16 bytes
- am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
- am_addr1 =3D PPCAMode_IR( 4, StackFramePtr(mode64) );
+ am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(False/*mode32*/) );
+ am_addr1 =3D PPCAMode_IR( 4, StackFramePtr(False/*mode32*/) );
=20
// store as F64
addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
@@ -2523,9 +2571,9 @@
=20
// load hi,lo as Ity_I32's
addInstr(env, PPCInstr_Load( 4, False, r_dstHi,
- am_addr0, mode64 ));
+ am_addr0, False/*mode32*/ ));
addInstr(env, PPCInstr_Load( 4, False, r_dstLo,
- am_addr1, mode64 ));
+ am_addr1, False/*mode32*/ ));
*rHi =3D r_dstHi;
*rLo =3D r_dstLo;
=20
@@ -2576,7 +2624,7 @@
PPCAMode* am_addr;
HReg r_dst =3D newVRegF(env);
vassert(e->Iex.Load.ty =3D=3D Ity_F32);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ am_addr =3D iselWordExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr));
return r_dst;
}
@@ -2692,7 +2740,7 @@
HReg r_dst =3D newVRegF(env);
PPCAMode* am_addr;
vassert(e->Iex.Load.ty =3D=3D Ity_F64);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ am_addr =3D iselWordExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr));
return r_dst;
}
@@ -2724,7 +2772,7 @@
=20
if (e->Iex.Binop.op =3D=3D Iop_I64toF64) {
HReg fr_dst =3D newVRegF(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
vassert(mode64);
=20
/* Set host rounding mode */
@@ -2766,7 +2814,7 @@
iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg);
return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
} else {
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
return mk_LoadR64toFPR( env, r_src );
}
}
@@ -2785,7 +2833,7 @@
if (ty =3D=3D Ity_F64
&& typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) =3D=3D Ity_I8=
) {
PPCCondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
- HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_cond =3D iselWordExpr_R(env, e->Iex.Mux0X.cond);
HReg frX =3D iselDblExpr(env, e->Iex.Mux0X.exprX);
HReg fr0 =3D iselDblExpr(env, e->Iex.Mux0X.expr0);
HReg fr_dst =3D newVRegF(env);
@@ -2849,7 +2897,7 @@
PPCAMode* am_addr;
HReg v_dst =3D newVRegV(env);
vassert(e->Iex.Load.ty =3D=3D Ity_V128);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ am_addr =3D iselWordExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, v_dst, am_addr));
return v_dst;
}
@@ -2914,7 +2962,7 @@
=20
case Iop_32UtoV128: {
HReg r_aligned16, r_zeros;
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
HReg dst =3D newVRegV(env);
PPCAMode *am_off0, *am_off4, *am_off8, *am_off12;
sub_from_sp( env, 32 ); // Move SP down
@@ -2986,8 +3034,8 @@
add_to_sp( env, 32 ); // Reset SP
return dst;
} else {
- HReg rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg rHi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
HReg dst =3D newVRegV(env);
HReg r_aligned16;
PPCAMode *am_off0, *am_off8;
@@ -3248,10 +3296,10 @@
( mode64 && (tya !=3D Ity_I64)) )
goto stmt_fail;
=20
- am_addr =3D iselIntExpr_AMode(env, stmt->Ist.Store.addr);
+ am_addr =3D iselWordExpr_AMode(env, stmt->Ist.Store.addr);
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16 || tyd =3D=3D Ity_I32 =
||
(mode64 && (tyd =3D=3D Ity_I64))) {
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Store.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.Store.data);
addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(tyd)),=20
am_addr, r_src, mode64 ));
return;
@@ -3282,7 +3330,7 @@
IRType ty =3D typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 ||
ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64)) {
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Put.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.Put.data);
PPCAMode* am_addr =3D PPCAMode_IR( stmt->Ist.Put.offset,
GuestStatePtr(mode64) );
addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(ty)),=20
@@ -3329,7 +3377,7 @@
stmt->Ist.PutI.ix, stmt->Ist.PutI.bias );
IRType ty =3D typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
if (ty =3D=3D Ity_I64) {
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.PutI.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.PutI.data);
addInstr(env, PPCInstr_Store( toUChar(8),
dst_am, r_src, mode64 ));
return;
@@ -3344,14 +3392,14 @@
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 ||
ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64)) {
HReg r_dst =3D lookupIRTemp(env, tmp);
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Tmp.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.Tmp.data);
addInstr(env, mk_iMOVds_RR( r_dst, r_src ));
return;
}
if (!mode64 && ty =3D=3D Ity_I64) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.Tmp.data);
- lookupIRTemp64( &r_dstHi, &r_dstLo, env, tmp);
+ lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
return;
@@ -3359,7 +3407,7 @@
if (mode64 && ty =3D=3D Ity_I128) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
iselInt...
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