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From: <sv...@va...> - 2006-01-04 10:53:10
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Author: cerion
Date: 2006-01-04 10:53:00 +0000 (Wed, 04 Jan 2006)
New Revision: 1531
Log:
ppc: re-enable mtfsb1 instruction.
Note: Only the rounding mode field of the FPSCR is supported.
- Reads from any other bits return zero.
- Writes to any other bits are ignored. Writes to 'exception control' b=
its or the 'non-ieee mode' bit results in an emulation warning.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-01-03 18:41:00 UTC (rev 1530)
+++ trunk/priv/guest-ppc/toIR.c 2006-01-04 10:53:00 UTC (rev 1531)
@@ -2058,10 +2058,6 @@
switch (reg) {
=20
case PPC_GST_FPSCR: {
- vassert((mask & 0x3) =3D=3D 0x3 || (mask & 0x3) =3D=3D 0x=
0);
- vassert((mask & 0xF000) =3D=3D 0xF000 || (mask & 0xF000) =3D=3D 0x=
0);
- /* all masks now refer to valid fields */
- =20
/* Vex-generated code expects the FPSCR to be set as follows:
all exceptions masked, round-to-nearest.
This corresponds to a FPSCR value of 0x0. */
@@ -2192,10 +2188,6 @@
=20
switch (reg) {
case PPC_GST_FPSCR: {
- vassert((mask & 0x3) =3D=3D 0x3 || (mask & 0x3) =3D=3D 0x=
0);
- vassert((mask & 0xF000) =3D=3D 0xF000 || (mask & 0xF000) =3D=3D 0x=
0);
- /* all masks now refer to valid fields */
-
/* Allow writes to Rounding Mode */
if (mask & 0x3) {
stmt( IRStmt_Put( OFFB_FPROUND,
@@ -6110,20 +6102,20 @@
}
=20
switch (opc2) {
-//zz case 0x026: { // mtfsb1 (Move to FPSCR Bit 1, PPC32 p479)
-//zz // Bit crbD of the FPSCR is set.
-//zz UChar crbD =3D ifieldRegDS(theInstr);
-//zz UInt b11to20 =3D IFIELD(theInstr, 11, 10);
-//zz=20
-//zz if (b11to20 !=3D 0) {
-//zz vex_printf("dis_fp_scr(ppc)(instr,mtfsb1)\n");
-//zz return False;
-//zz }
-//zz DIP("mtfsb1%s crb%d \n", flag_rC ? ".":"", crbD);
-//zz putGST_masked( PPC_GST_FPSCR, mkU32(1<<(31-crbD)), 1<<(31-crb=
D) );
-//zz break;
-//zz }
-//zz=20
+ case 0x026: { // mtfsb1 (Move to FPSCR Bit 1, PPC32 p479)
+ // Bit crbD of the FPSCR is set.
+ UChar crbD =3D ifieldRegDS(theInstr);
+ UInt b11to20 =3D IFIELD(theInstr, 11, 10);
+
+ if (b11to20 !=3D 0) {
+ vex_printf("dis_fp_scr(ppc)(instr,mtfsb1)\n");
+ return False;
+ }
+ DIP("mtfsb1%s crb%d \n", flag_rC ? ".":"", crbD);
+ putGST_masked( PPC_GST_FPSCR, mkU32(1<<(31-crbD)), 1<<(31-crbD) );
+ break;
+ }
+
//zz case 0x040: { // mcrfs (Move to Condition Register from FPSCR, P=
PC32 p465)
//zz UChar crfD =3D toUChar( IFIELD( theInstr, 23, 3 ) );
//zz UChar b21to22 =3D toUChar( IFIELD( theInstr, 21, 2 ) );
@@ -8582,7 +8574,7 @@
goto decode_failure;
=20
/* Floating Point Status/Control Register Instructions */ =20
-//zz case 0x026: // mtfsb1
+ case 0x026: // mtfsb1
//zz case 0x040: // mcrfs
case 0x046: // mtfsb0
case 0x086: // mtfsfi
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