|
From: <sv...@va...> - 2005-12-13 12:02:36
|
Author: cerion
Date: 2005-12-13 12:02:26 +0000 (Tue, 13 Dec 2005)
New Revision: 1487
Log:
Added 'Bool mode64' to the various backend functions, to distinguish 32/6=
4bit arch's.
This will be needed for the ppc32/64 backend.
Modified:
trunk/priv/guest-generic/bb_to_IR.c
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
trunk/priv/host-generic/h_generic_regs.h
trunk/priv/host-generic/reg_alloc2.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
trunk/priv/host-ppc32/isel.c
trunk/priv/host-x86/hdefs.c
trunk/priv/host-x86/hdefs.h
trunk/priv/host-x86/isel.c
trunk/priv/main/vex_main.c
Modified: trunk/priv/guest-generic/bb_to_IR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-generic/bb_to_IR.c 2005-12-07 22:19:36 UTC (rev 1486=
)
+++ trunk/priv/guest-generic/bb_to_IR.c 2005-12-13 12:02:26 UTC (rev 1487=
)
@@ -274,8 +274,8 @@
vassert(resteerOKfn(dres.continueAt));
delta =3D dres.continueAt - guest_IP_bbstart;
/* we now have to start a new extent slot. */
- vge->n_used++;
- vassert(vge->n_used <=3D 3);
+ vge->n_used++;
+ vassert(vge->n_used <=3D 3);
vge->base[vge->n_used-1] =3D dres.continueAt;
vge->len[vge->n_used-1] =3D 0;
n_resteers++;
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-amd64/hdefs.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -1019,8 +1019,9 @@
return i;
}
=20
-void ppAMD64Instr ( AMD64Instr* i )=20
+void ppAMD64Instr ( AMD64Instr* i, Bool mode64 )=20
{
+ vassert(mode64 =3D=3D True);
switch (i->tag) {
case Ain_Imm64:=20
vex_printf("movabsq $0x%llx,", i->Ain.Imm64.imm64);
@@ -1335,9 +1336,10 @@
=20
/* --------- Helpers for register allocation. --------- */
=20
-void getRegUsage_AMD64Instr ( HRegUsage* u, AMD64Instr* i )
+void getRegUsage_AMD64Instr ( HRegUsage* u, AMD64Instr* i, Bool mode64 )
{
Bool unary;
+ vassert(mode64 =3D=3D True);
initHRegUsage(u);
switch (i->tag) {
case Ain_Imm64:
@@ -1607,7 +1609,7 @@
addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
return;
default:
- ppAMD64Instr(i);
+ ppAMD64Instr(i, mode64);
vpanic("getRegUsage_AMD64Instr");
}
}
@@ -1618,8 +1620,9 @@
*r =3D lookupHRegRemap(m, *r);
}
=20
-void mapRegs_AMD64Instr ( HRegRemap* m, AMD64Instr* i )
+void mapRegs_AMD64Instr ( HRegRemap* m, AMD64Instr* i, Bool mode64 )
{
+ vassert(mode64 =3D=3D True);
switch (i->tag) {
case Ain_Imm64:
mapReg(m, &i->Ain.Imm64.dst);
@@ -1781,7 +1784,7 @@
mapReg(m, &i->Ain.SseShuf.dst);
return;
default:
- ppAMD64Instr(i);
+ ppAMD64Instr(i, mode64);
vpanic("mapRegs_AMD64Instr");
}
}
@@ -1818,11 +1821,12 @@
register allocator. Note it's critical these don't write the
condition codes. */
=20
-AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB )
+AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB, Bool mode64 )
{
AMD64AMode* am;
vassert(offsetB >=3D 0);
vassert(!hregIsVirtual(rreg));
+ vassert(mode64 =3D=3D True);
am =3D AMD64AMode_IR(offsetB, hregAMD64_RBP());
=20
switch (hregClass(rreg)) {
@@ -1836,11 +1840,12 @@
}
}
=20
-AMD64Instr* genReload_AMD64 ( HReg rreg, Int offsetB )
+AMD64Instr* genReload_AMD64 ( HReg rreg, Int offsetB, Bool mode64 )
{
AMD64AMode* am;
vassert(offsetB >=3D 0);
vassert(!hregIsVirtual(rreg));
+ vassert(mode64 =3D=3D True);
am =3D AMD64AMode_IR(offsetB, hregAMD64_RBP());
switch (hregClass(rreg)) {
case HRcInt64:
@@ -2195,7 +2200,7 @@
Note that buf is not the insn's final place, and therefore it is
imperative to emit position-independent code. */
=20
-Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
+Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i, Bool mode64 )
{
UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, su=
bopc;
UInt xtra;
@@ -2205,13 +2210,14 @@
UChar* ptmp;
Int j;
vassert(nbuf >=3D 32);
+ vassert(mode64 =3D=3D True);
=20
/* Wrap an integer as a int register, for use assembling
GrpN insns, in which the greg field is used as a sub-opcode
and does not really contain a register. */
# define fake(_n) mkHReg((_n), HRcInt64, False)
=20
- /* vex_printf("asm "); ppAMD64Instr(i); vex_printf("\n"); */
+ /* vex_printf("asm "); ppAMD64Instr(i, mode64); vex_printf("\n"); */
=20
switch (i->tag) {
=20
@@ -3337,7 +3343,7 @@
}
=20
bad:
- ppAMD64Instr(i);
+ ppAMD64Instr(i, mode64);
vpanic("emit_AMD64Instr");
/*NOTREACHED*/
=20
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-amd64/hdefs.h 2005-12-13 12:02:26 UTC (rev 1487)
@@ -708,16 +708,16 @@
extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst=
);
=20
=20
-extern void ppAMD64Instr ( AMD64Instr* );
+extern void ppAMD64Instr ( AMD64Instr*, Bool );
=20
/* Some functions that insulate the register allocator from details
of the underlying instruction set. */
-extern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr* );
-extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr* );
+extern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bo=
ol );
+extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bo=
ol );
extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* )=
;
-extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64=
Instr* );
-extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset );
-extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset );
+extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64=
Instr*, Bool );
+extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool=
);
+extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool=
);
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArchInfo* );
=20
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-amd64/isel.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -171,7 +171,7 @@
{
addHInstr(env->code, instr);
if (vex_traceflags & VEX_TRACE_VCODE) {
- ppAMD64Instr(instr);
+ ppAMD64Instr(instr, False);
vex_printf("\n");
}
}
Modified: trunk/priv/host-generic/h_generic_regs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-generic/h_generic_regs.h 2005-12-07 22:19:36 UTC (rev=
1486)
+++ trunk/priv/host-generic/h_generic_regs.h 2005-12-13 12:02:26 UTC (rev=
1487)
@@ -253,20 +253,23 @@
Bool (*isMove) (HInstr*, HReg*, HReg*),
=20
/* Get info about register usage in this insn. */
- void (*getRegUsage) (HRegUsage*, HInstr*),
+ void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
=20
/* Apply a reg-reg mapping to an insn. */
- void (*mapRegs) (HRegRemap*, HInstr*),
+ void (*mapRegs) (HRegRemap*, HInstr*, Bool),
=20
/* Return an insn to spill/restore a real reg to a spill slot
offset. */
- HInstr* (*genSpill) ( HReg, Int ),
- HInstr* (*genReload) ( HReg, Int ),
+ HInstr* (*genSpill) ( HReg, Int, Bool ),
+ HInstr* (*genReload) ( HReg, Int, Bool ),
Int guest_sizeB,
=20
/* For debug printing only. */
- void (*ppInstr) ( HInstr* ),
- void (*ppReg) ( HReg )
+ void (*ppInstr) ( HInstr*, Bool ),
+ void (*ppReg) ( HReg ),
+
+ /* 32/64bit mode */
+ Bool mode64
);
=20
=20
Modified: trunk/priv/host-generic/reg_alloc2.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-generic/reg_alloc2.c 2005-12-07 22:19:36 UTC (rev 148=
6)
+++ trunk/priv/host-generic/reg_alloc2.c 2005-12-13 12:02:26 UTC (rev 148=
7)
@@ -155,14 +155,15 @@
=20
/* Does this instruction mention a particular reg? */
static Bool instrMentionsReg (=20
- void (*getRegUsage) (HRegUsage*, HInstr*),
+ void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
HInstr* instr,=20
- HReg r=20
+ HReg r,
+ Bool mode64
)
{
Int i;
HRegUsage reg_usage;
- (*getRegUsage)(®_usage, instr);
+ (*getRegUsage)(®_usage, instr, mode64);
for (i =3D 0; i < reg_usage.n_used; i++)
if (reg_usage.hreg[i] =3D=3D r)
return True;
@@ -184,11 +185,12 @@
spill, or -1 if none was found. */
static
Int findMostDistantlyMentionedVReg (=20
- void (*getRegUsage) (HRegUsage*, HInstr*),
+ void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
HInstrArray* instrs_in,
Int search_from_instr,
RRegState* state,
- Int n_state
+ Int n_state,
+ Bool mode64
)
{
Int k, m;
@@ -201,7 +203,7 @@
vassert(state[k].disp =3D=3D Bound);
for (m =3D search_from_instr; m < instrs_in->arr_used; m++) {
if (instrMentionsReg(getRegUsage,=20
- instrs_in->arr[m], state[k].vreg))
+ instrs_in->arr[m], state[k].vreg, mode64))
break;
}
if (m > furthest) {
@@ -258,23 +260,26 @@
=20
/* Return True iff the given insn is a reg-reg move, in which
case also return the src and dst regs. */
- Bool (*isMove) (HInstr*, HReg*, HReg*),
+ Bool (*isMove) ( HInstr*, HReg*, HReg* ),
=20
/* Get info about register usage in this insn. */
- void (*getRegUsage) (HRegUsage*, HInstr*),
+ void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ),
=20
/* Apply a reg-reg mapping to an insn. */
- void (*mapRegs) (HRegRemap*, HInstr*),
+ void (*mapRegs) ( HRegRemap*, HInstr*, Bool ),
=20
/* Return an insn to spill/restore a real reg to a spill slot
byte offset. */
- HInstr* (*genSpill) ( HReg, Int ),
- HInstr* (*genReload) ( HReg, Int ),
+ HInstr* (*genSpill) ( HReg, Int, Bool ),
+ HInstr* (*genReload) ( HReg, Int, Bool ),
Int guest_sizeB,
=20
/* For debug printing only. */
- void (*ppInstr) ( HInstr* ),
- void (*ppReg) ( HReg )
+ void (*ppInstr) ( HInstr*, Bool ),
+ void (*ppReg) ( HReg ),
+
+ /* 32/64bit mode */
+ Bool mode64
)
{
# define N_SPILL64S (LibVEX_N_SPILL_BYTES / 8)
@@ -336,7 +341,7 @@
HInstr* _tmp =3D (_instr); \
if (DEBUG_REGALLOC) { \
vex_printf("** "); \
- (*ppInstr)(_tmp); \
+ (*ppInstr)(_tmp, mode64); \
vex_printf("\n\n"); \
} \
addHInstr ( instrs_out, _tmp ); \
@@ -451,11 +456,11 @@
=20
for (ii =3D 0; ii < instrs_in->arr_used; ii++) {
=20
- (*getRegUsage)( ®_usage, instrs_in->arr[ii] );
+ (*getRegUsage)( ®_usage, instrs_in->arr[ii], mode64 );
=20
# if 0
vex_printf("\n%d stage1: ", ii);
- (*ppInstr)(instrs_in->arr[ii]);
+ (*ppInstr)(instrs_in->arr[ii], mode64);
vex_printf("\n");
ppHRegUsage(®_usage);
# endif
@@ -472,7 +477,7 @@
k =3D hregNumber(vreg);
if (k < 0 || k >=3D n_vregs) {
vex_printf("\n");
- (*ppInstr)(instrs_in->arr[ii]);
+ (*ppInstr)(instrs_in->arr[ii], mode64);
vex_printf("\n");
vex_printf("vreg %d, n_vregs %d\n", k, n_vregs);
vpanic("doRegisterAllocation: out-of-range vreg");
@@ -561,7 +566,7 @@
(*ppReg)(available_real_regs[k]);
vex_printf("\n");
vex_printf("\nOFFENDING instr =3D ");
- (*ppInstr)(instrs_in->arr[ii]);
+ (*ppInstr)(instrs_in->arr[ii], mode64);
vex_printf("\n");
vpanic("doRegisterAllocation: "
"first event for rreg is Read");
@@ -574,7 +579,7 @@
(*ppReg)(available_real_regs[k]);
vex_printf("\n");
vex_printf("\nOFFENDING instr =3D ");
- (*ppInstr)(instrs_in->arr[ii]);
+ (*ppInstr)(instrs_in->arr[ii], mode64);
vex_printf("\n");
vpanic("doRegisterAllocation: "
"first event for rreg is Modify");
@@ -786,7 +791,7 @@
# if DEBUG_REGALLOC
vex_printf("\n=3D=3D=3D=3D----=3D=3D=3D=3D---- Insn %d ----=3D=3D=3D=
=3D----=3D=3D=3D=3D\n", ii);
vex_printf("---- ");
- (*ppInstr)(instrs_in->arr[ii]);
+ (*ppInstr)(instrs_in->arr[ii], mode64);
vex_printf("\n\nInitial state:\n");
PRINT_STATE;
vex_printf("\n");
@@ -1009,7 +1014,8 @@
if (vreg_lrs[m].dead_before > ii) {
vassert(vreg_lrs[m].reg_class !=3D HRcINVALID);
EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
- vreg_lrs[m].spill_offset ) );
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
}
}
rreg_state[k].disp =3D Unavail;
@@ -1033,7 +1039,7 @@
We also build up the final vreg->rreg mapping to be applied
to the insn. */
=20
- (*getRegUsage)( ®_usage, instrs_in->arr[ii] );
+ (*getRegUsage)( ®_usage, instrs_in->arr[ii], mode64 );
=20
initHRegRemap(&remap);
=20
@@ -1098,7 +1104,8 @@
if (reg_usage.mode[j] !=3D HRmWrite) {
vassert(vreg_lrs[m].reg_class !=3D HRcINVALID);
EMIT_INSTR( (*genReload)( rreg_state[k].rreg,
- vreg_lrs[m].spill_offset ) );
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
}
continue;
}
@@ -1133,7 +1140,7 @@
of consequent reloads required. */
spillee
=3D findMostDistantlyMentionedVReg (=20
- getRegUsage, instrs_in, ii+1, rreg_state, n_rregs );
+ getRegUsage, instrs_in, ii+1, rreg_state, n_rregs, mode=
64 );
=20
if (spillee =3D=3D -1) {
/* Hmmmmm. There don't appear to be any spill candidates.
@@ -1161,7 +1168,8 @@
vassert(vreg_lrs[m].dead_before > ii);
vassert(vreg_lrs[m].reg_class !=3D HRcINVALID);
EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg,
- vreg_lrs[m].spill_offset ) );
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
=20
/* Update the rreg_state to reflect the new assignment for this
rreg. */
@@ -1177,7 +1185,8 @@
if (reg_usage.mode[j] !=3D HRmWrite) {
vassert(vreg_lrs[m].reg_class !=3D HRcINVALID);
EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg,
- vreg_lrs[m].spill_offset ) );
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
}
=20
/* So after much twisting and turning, we have vreg mapped to
@@ -1198,7 +1207,7 @@
*/
=20
/* NOTE, DESTRUCTIVELY MODIFIES instrs_in->arr[ii]. */
- (*mapRegs)( &remap, instrs_in->arr[ii] );
+ (*mapRegs)( &remap, instrs_in->arr[ii], mode64 );
EMIT_INSTR( instrs_in->arr[ii] );
=20
# if DEBUG_REGALLOC
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-ppc32/hdefs.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -189,7 +189,7 @@
HReg hregPPC32_VR30 ( void ) { return mkHReg(30, HRcVec128, False); }
HReg hregPPC32_VR31 ( void ) { return mkHReg(31, HRcVec128, False); }
=20
-void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr )
+void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr, Bool mode64 )
{
UInt i=3D0;
*nregs =3D 90 - 24 - 24;
@@ -1088,7 +1088,7 @@
}
}
=20
-void ppPPC32Instr ( PPC32Instr* i )
+void ppPPC32Instr ( PPC32Instr* i, Bool mode64 )
{
switch (i->tag) {
case Pin_LI32:
@@ -1510,7 +1510,7 @@
=20
/* --------- Helpers for register allocation. --------- */
=20
-void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i )
+void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i, Bool mode64 )
{
initHRegUsage(u);
switch (i->tag) {
@@ -1734,18 +1734,18 @@
return;
=20
default:
- ppPPC32Instr(i);
+ ppPPC32Instr(i, mode64);
vpanic("getRegUsage_PPC32Instr");
}
}
=20
/* local helper */
-static void mapReg(HRegRemap* m, HReg* r)
+static void mapReg( HRegRemap* m, HReg* r )
{
*r =3D lookupHRegRemap(m, *r);
}
=20
-void mapRegs_PPC32Instr (HRegRemap* m, PPC32Instr* i)
+void mapRegs_PPC32Instr ( HRegRemap* m, PPC32Instr* i, Bool mode64 )
{
switch (i->tag) {
case Pin_LI32:
@@ -1907,7 +1907,7 @@
return;
=20
default:
- ppPPC32Instr(i);
+ ppPPC32Instr(i, mode64);
vpanic("mapRegs_PPC32Instr");
}
}
@@ -1946,7 +1946,7 @@
/* Generate ppc32 spill/reload instructions under the direction of the
register allocator. Note it's critical these don't write the
condition codes. */
-PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )
+PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB, Bool mode64 )
{
PPC32AMode* am;
vassert(!hregIsVirtual(rreg));
@@ -1966,7 +1966,7 @@
}
}
=20
-PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB )
+PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB, Bool mode64 )
{
PPC32AMode* am;
vassert(!hregIsVirtual(rreg));
@@ -2286,13 +2286,13 @@
Note that buf is not the insn's final place, and therefore it is
imperative to emit position-independent code. */
=20
-Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i )
+Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i, Bool mode64 )
{
UChar* p =3D &buf[0];
UChar* ptmp =3D p;
vassert(nbuf >=3D 32);
=20
-// vex_printf("asm ");ppPPC32Instr(i); vex_printf("\n");
+// vex_printf("asm ");ppPPC32Instr(i, mode64); vex_printf("\n");
=20
switch (i->tag) {
=20
@@ -3295,7 +3295,7 @@
=20
bad:
vex_printf("\n=3D> ");
- ppPPC32Instr(i);
+ ppPPC32Instr(i, mode64);
vpanic("emit_PPC32Instr");
/*NOTREACHED*/
=20
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-ppc32/hdefs.h 2005-12-13 12:02:26 UTC (rev 1487)
@@ -774,17 +774,17 @@
extern PPC32Instr* PPC32Instr_AvCMov ( PPC32CondCode, HReg dst, HReg=
src );
extern PPC32Instr* PPC32Instr_AvLdVSCR ( HReg src );
=20
-extern void ppPPC32Instr ( PPC32Instr* );
+extern void ppPPC32Instr ( PPC32Instr*, Bool mode64 );
=20
/* Some functions that insulate the register allocator from details
of the underlying instruction set. */
-extern void getRegUsage_PPC32Instr ( HRegUsage*, PPC32Instr* );
-extern void mapRegs_PPC32Instr ( HRegRemap*, PPC32Instr* );
+extern void getRegUsage_PPC32Instr ( HRegUsage*, PPC32Instr*, Bo=
ol mode64 );
+extern void mapRegs_PPC32Instr ( HRegRemap*, PPC32Instr* , B=
ool mode64);
extern Bool isMove_PPC32Instr ( PPC32Instr*, HReg*, HReg* )=
;
-extern Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32=
Instr* );
-extern PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )=
;
-extern PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB )=
;
-extern void getAllocableRegs_PPC32 ( Int*, HReg** );
+extern Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32=
Instr*, Bool mode64 );
+extern PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB, =
Bool mode64 );
+extern PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB, =
Bool mode64 );
+extern void getAllocableRegs_PPC32 ( Int*, HReg**, Bool mode64 )=
;
extern HInstrArray* iselBB_PPC32 ( IRBB*, VexArchInfo* );
=20
#endif /* ndef __LIBVEX_HOST_PPC32_HDEFS_H */
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-ppc32/isel.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -209,7 +209,7 @@
{
addHInstr(env->code, instr);
if (vex_traceflags & VEX_TRACE_VCODE) {
- ppPPC32Instr(instr);
+ ppPPC32Instr(instr, False);
vex_printf("\n");
}
}
Modified: trunk/priv/host-x86/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/hdefs.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-x86/hdefs.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -877,7 +877,8 @@
return i;
}
=20
-void ppX86Instr ( X86Instr* i ) {
+void ppX86Instr ( X86Instr* i, Bool mode64 ) {
+ vassert(mode64 =3D=3D False);
switch (i->tag) {
case Xin_Alu32R:
vex_printf("%sl ", showX86AluOp(i->Xin.Alu32R.op));
@@ -1128,9 +1129,10 @@
=20
/* --------- Helpers for register allocation. --------- */
=20
-void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i)
+void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i, Bool mode64)
{
Bool unary;
+ vassert(mode64 =3D=3D False);
initHRegUsage(u);
switch (i->tag) {
case Xin_Alu32R:
@@ -1348,19 +1350,20 @@
addHRegUse(u, HRmWrite, i->Xin.SseShuf.dst);
return;
default:
- ppX86Instr(i);
+ ppX86Instr(i, False);
vpanic("getRegUsage_X86Instr");
}
}
=20
/* local helper */
-static void mapReg(HRegRemap* m, HReg* r)
+static void mapReg( HRegRemap* m, HReg* r )
{
*r =3D lookupHRegRemap(m, *r);
}
=20
-void mapRegs_X86Instr (HRegRemap* m, X86Instr* i)
+void mapRegs_X86Instr ( HRegRemap* m, X86Instr* i, Bool mode64 )
{
+ vassert(mode64 =3D=3D False);
switch (i->tag) {
case Xin_Alu32R:
mapRegs_X86RMI(m, i->Xin.Alu32R.src);
@@ -1493,7 +1496,7 @@
mapReg(m, &i->Xin.SseShuf.dst);
return;
default:
- ppX86Instr(i);
+ ppX86Instr(i, mode64);
vpanic("mapRegs_X86Instr");
}
}
@@ -1537,11 +1540,12 @@
register allocator. Note it's critical these don't write the
condition codes. */
=20
-X86Instr* genSpill_X86 ( HReg rreg, Int offsetB )
+X86Instr* genSpill_X86 ( HReg rreg, Int offsetB, Bool mode64 )
{
X86AMode* am;
vassert(offsetB >=3D 0);
vassert(!hregIsVirtual(rreg));
+ vassert(mode64 =3D=3D False);
am =3D X86AMode_IR(offsetB, hregX86_EBP());
=20
switch (hregClass(rreg)) {
@@ -1557,11 +1561,12 @@
}
}
=20
-X86Instr* genReload_X86 ( HReg rreg, Int offsetB )
+X86Instr* genReload_X86 ( HReg rreg, Int offsetB, Bool mode64 )
{
X86AMode* am;
vassert(offsetB >=3D 0);
vassert(!hregIsVirtual(rreg));
+ vassert(mode64 =3D=3D False);
am =3D X86AMode_IR(offsetB, hregX86_EBP());
switch (hregClass(rreg)) {
case HRcInt32:
@@ -1827,7 +1832,7 @@
Note that buf is not the insn's final place, and therefore it is
imperative to emit position-independent code. */
=20
-Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i )
+Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i, Bool mode64 )
{
UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc=
;
=20
@@ -1835,13 +1840,14 @@
UChar* p =3D &buf[0];
UChar* ptmp;
vassert(nbuf >=3D 32);
+ vassert(mode64 =3D=3D False);
=20
/* Wrap an integer as a int register, for use assembling
GrpN insns, in which the greg field is used as a sub-opcode
and does not really contain a register. */
# define fake(_n) mkHReg((_n), HRcInt32, False)
=20
- /* vex_printf("asm ");ppX86Instr(i); vex_printf("\n"); */
+ /* vex_printf("asm ");ppX86Instr(i, mode64); vex_printf("\n"); */
=20
switch (i->tag) {
=20
@@ -2815,7 +2821,7 @@
}
=20
bad:
- ppX86Instr(i);
+ ppX86Instr(i, mode64);
vpanic("emit_X86Instr");
/*NOTREACHED*/
=20
Modified: trunk/priv/host-x86/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/hdefs.h 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-x86/hdefs.h 2005-12-13 12:02:26 UTC (rev 1487)
@@ -653,16 +653,16 @@
extern X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst );
=20
=20
-extern void ppX86Instr ( X86Instr* );
+extern void ppX86Instr ( X86Instr*, Bool );
=20
/* Some functions that insulate the register allocator from details
of the underlying instruction set. */
-extern void getRegUsage_X86Instr ( HRegUsage*, X86Instr* );
-extern void mapRegs_X86Instr ( HRegRemap*, X86Instr* );
+extern void getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool )=
;
+extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool )=
;
extern Bool isMove_X86Instr ( X86Instr*, HReg*, HReg* );
-extern Int emit_X86Instr ( UChar* buf, Int nbuf, X86Inst=
r* );
-extern X86Instr* genSpill_X86 ( HReg rreg, Int offset );
-extern X86Instr* genReload_X86 ( HReg rreg, Int offset );
+extern Int emit_X86Instr ( UChar* buf, Int nbuf, X86Inst=
r*, Bool );
+extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool )=
;
+extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool )=
;
extern void getAllocableRegs_X86 ( Int*, HReg** );
extern HInstrArray* iselBB_X86 ( IRBB*, VexArchInfo* );
=20
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/host-x86/isel.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -183,7 +183,7 @@
{
addHInstr(env->code, instr);
if (vex_traceflags & VEX_TRACE_VCODE) {
- ppX86Instr(instr);
+ ppX86Instr(instr, False);
vex_printf("\n");
}
}
Modified: trunk/priv/main/vex_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/main/vex_main.c 2005-12-07 22:19:36 UTC (rev 1486)
+++ trunk/priv/main/vex_main.c 2005-12-13 12:02:26 UTC (rev 1487)
@@ -215,15 +215,15 @@
from the target instruction set. */
HReg* available_real_regs;
Int n_available_real_regs;
- Bool (*isMove) (HInstr*, HReg*, HReg*);
- void (*getRegUsage) (HRegUsage*, HInstr*);
- void (*mapRegs) (HRegRemap*, HInstr*);
- HInstr* (*genSpill) ( HReg, Int );
- HInstr* (*genReload) ( HReg, Int );
- void (*ppInstr) ( HInstr* );
+ Bool (*isMove) ( HInstr*, HReg*, HReg* );
+ void (*getRegUsage) ( HRegUsage*, HInstr*, Bool );
+ void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
+ HInstr* (*genSpill) ( HReg, Int, Bool );
+ HInstr* (*genReload) ( HReg, Int, Bool );
+ void (*ppInstr) ( HInstr*, Bool );
void (*ppReg) ( HReg );
HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* );
- Int (*emit) ( UChar*, Int, HInstr* );
+ Int (*emit) ( UChar*, Int, HInstr*, Bool );
IRExpr* (*specHelper) ( HChar*, IRExpr** );
Bool (*preciseMemExnsFn) ( Int, Int );
=20
@@ -239,6 +239,7 @@
UChar insn_bytes[32];
IRType guest_word_type;
IRType host_word_type;
+ Bool mode64;
=20
guest_layout =3D NULL;
available_real_regs =3D NULL;
@@ -259,6 +260,7 @@
host_word_type =3D Ity_INVALID;
offB_TISTART =3D 0;
offB_TILEN =3D 0;
+ mode64 =3D False;
=20
vex_traceflags =3D traceflags;
=20
@@ -272,17 +274,18 @@
switch (arch_host) {
=20
case VexArchX86:
+ mode64 =3D False;
getAllocableRegs_X86 ( &n_available_real_regs,
&available_real_regs );
isMove =3D (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr;
- getRegUsage =3D (void(*)(HRegUsage*,HInstr*)) getRegUsage_X86In=
str;
- mapRegs =3D (void(*)(HRegRemap*,HInstr*)) mapRegs_X86Instr;
- genSpill =3D (HInstr*(*)(HReg,Int)) genSpill_X86;
- genReload =3D (HInstr*(*)(HReg,Int)) genReload_X86;
- ppInstr =3D (void(*)(HInstr*)) ppX86Instr;
+ getRegUsage =3D (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage=
_X86Instr;
+ mapRegs =3D (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86=
Instr;
+ genSpill =3D (HInstr*(*)(HReg,Int, Bool)) genSpill_X86;
+ genReload =3D (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
+ ppInstr =3D (void(*)(HInstr*, Bool)) ppX86Instr;
ppReg =3D (void(*)(HReg)) ppHRegX86;
iselBB =3D iselBB_X86;
- emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_X86Instr;
+ emit =3D (Int(*)(UChar*,Int,HInstr*, Bool)) emit_X86Inst=
r;
host_is_bigendian =3D False;
host_word_type =3D Ity_I32;
vassert(archinfo_host->subarch =3D=3D VexSubArchX86_sse0
@@ -291,34 +294,36 @@
break;
=20
case VexArchAMD64:
+ mode64 =3D True;
getAllocableRegs_AMD64 ( &n_available_real_regs,
&available_real_regs );
isMove =3D (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Inst=
r;
- getRegUsage =3D (void(*)(HRegUsage*,HInstr*)) getRegUsage_AMD64=
Instr;
- mapRegs =3D (void(*)(HRegRemap*,HInstr*)) mapRegs_AMD64Inst=
r;
- genSpill =3D (HInstr*(*)(HReg,Int)) genSpill_AMD64;
- genReload =3D (HInstr*(*)(HReg,Int)) genReload_AMD64;
- ppInstr =3D (void(*)(HInstr*)) ppAMD64Instr;
+ getRegUsage =3D (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage=
_AMD64Instr;
+ mapRegs =3D (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD=
64Instr;
+ genSpill =3D (HInstr*(*)(HReg,Int, Bool)) genSpill_AMD64;
+ genReload =3D (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64;
+ ppInstr =3D (void(*)(HInstr*, Bool)) ppAMD64Instr;
ppReg =3D (void(*)(HReg)) ppHRegAMD64;
iselBB =3D iselBB_AMD64;
- emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_AMD64Instr;
+ emit =3D (Int(*)(UChar*,Int,HInstr*, Bool)) emit_AMD64In=
str;
host_is_bigendian =3D False;
host_word_type =3D Ity_I64;
vassert(archinfo_host->subarch =3D=3D VexSubArch_NONE);
break;
=20
case VexArchPPC32:
+ mode64 =3D False;
getAllocableRegs_PPC32 ( &n_available_real_regs,
- &available_real_regs );
+ &available_real_regs, mode64 );
isMove =3D (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPC32Inst=
r;
- getRegUsage =3D (void(*)(HRegUsage*,HInstr*)) getRegUsage_PPC32=
Instr;
- mapRegs =3D (void(*)(HRegRemap*,HInstr*)) mapRegs_PPC32Inst=
r;
- genSpill =3D (HInstr*(*)(HReg,Int)) genSpill_PPC32;
- genReload =3D (HInstr*(*)(HReg,Int)) genReload_PPC32;
- ppInstr =3D (void(*)(HInstr*)) ppPPC32Instr;
+ getRegUsage =3D (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_=
PPC32Instr;
+ mapRegs =3D (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPC3=
2Instr;
+ genSpill =3D (HInstr*(*)(HReg,Int,Bool)) genSpill_PPC32;
+ genReload =3D (HInstr*(*)(HReg,Int,Bool)) genReload_PPC32;
+ ppInstr =3D (void(*)(HInstr*,Bool)) ppPPC32Instr;
ppReg =3D (void(*)(HReg)) ppHRegPPC32;
iselBB =3D iselBB_PPC32;
- emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_PPC32Instr;
+ emit =3D (Int(*)(UChar*,Int,HInstr*,Bool)) emit_PPC32Ins=
tr;
host_is_bigendian =3D True;
host_word_type =3D Ity_I32;
vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_I
@@ -553,7 +558,7 @@
if (vex_traceflags & VEX_TRACE_VCODE) {
for (i =3D 0; i < vcode->arr_used; i++) {
vex_printf("%3d ", i);
- ppInstr(vcode->arr[i]);
+ ppInstr(vcode->arr[i], mode64);
vex_printf("\n");
}
vex_printf("\n");
@@ -564,7 +569,7 @@
n_available_real_regs,
isMove, getRegUsage, mapRegs,=20
genSpill, genReload, guest_sizeB,
- ppInstr, ppReg );
+ ppInstr, ppReg, mode64 );
=20
vexAllocSanityCheck();
=20
@@ -574,7 +579,7 @@
"------------------------\n\n");
for (i =3D 0; i < rcode->arr_used; i++) {
vex_printf("%3d ", i);
- ppInstr(rcode->arr[i]);
+ ppInstr(rcode->arr[i], mode64);
vex_printf("\n");
}
vex_printf("\n");
@@ -594,10 +599,10 @@
out_used =3D 0; /* tracks along the host_bytes array */
for (i =3D 0; i < rcode->arr_used; i++) {
if (vex_traceflags & VEX_TRACE_ASM) {
- ppInstr(rcode->arr[i]);
+ ppInstr(rcode->arr[i], mode64);
vex_printf("\n");
}
- j =3D (*emit)( insn_bytes, 32, rcode->arr[i] );
+ j =3D (*emit)( insn_bytes, 32, rcode->arr[i], mode64 );
if (vex_traceflags & VEX_TRACE_ASM) {
for (k =3D 0; k < j; k++)
if (insn_bytes[k] < 16)
|