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From: <sv...@va...> - 2005-12-06 23:48:00
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Author: njn
Date: 2005-12-06 23:47:58 +0000 (Tue, 06 Dec 2005)
New Revision: 5304
Log:
Fix bug in STOREV4 fast case -- if one or more byte in a word is addressa=
ble
it doesn't imply that all four are.
Modified:
branches/COMPVBITS/memcheck/mc_main.c
Modified: branches/COMPVBITS/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/COMPVBITS/memcheck/mc_main.c 2005-12-06 23:19:39 UTC (rev 53=
03)
+++ branches/COMPVBITS/memcheck/mc_main.c 2005-12-06 23:47:58 UTC (rev 53=
04)
@@ -1749,6 +1749,8 @@
=20
PROF_EVENT(210, "mc_STOREV8");
=20
+ // XXX: this slow case seems to be marginally faster than the fast ca=
se!
+ // Investigate further.
if (VG_DEBUG_MEMORY >=3D 2) {
mc_STOREVn_slow( aA, 8, vbytes, isBigEndian );
return;
@@ -1917,20 +1919,20 @@
if (VGM_WORD32_VALID =3D=3D vbytes) {
if (vabits32 =3D=3D (UInt)MC_BITS32_READABLE) {
return;
- } else if (!is_distinguished_sm(sm) && MC_BITS32_NOACCESS !=3D vab=
its32) {
+ } else if (!is_distinguished_sm(sm) && MC_BITS32_WRITABLE =3D=3D v=
abits32) {
sm->vabits32[sm_off] =3D (UInt)MC_BITS32_READABLE;
} else {
- // unaddressable, or distinguished and changing state
+ // not readable/writable, or distinguished and changing state
PROF_EVENT(232, "mc_STOREV4-slow2");
mc_STOREVn_slow( aA, 4, (ULong)vbytes, isBigEndian );
}
} else if (VGM_WORD32_INVALID =3D=3D vbytes) {
if (vabits32 =3D=3D (UInt)MC_BITS32_WRITABLE) {
return;
- } else if (!is_distinguished_sm(sm) && MC_BITS32_NOACCESS !=3D vab=
its32) {
+ } else if (!is_distinguished_sm(sm) && MC_BITS32_READABLE =3D=3D v=
abits32) {
sm->vabits32[sm_off] =3D (UInt)MC_BITS32_WRITABLE;
} else {
- // unaddressable, or distinguished and changing state
+ // not readable/writable, or distinguished and changing state
PROF_EVENT(233, "mc_STOREV4-slow3");
mc_STOREVn_slow( aA, 4, (ULong)vbytes, isBigEndian );
}
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