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From: <sv...@va...> - 2005-12-01 19:05:50
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Author: cerion
Date: 2005-12-01 19:05:41 +0000 (Thu, 01 Dec 2005)
New Revision: 5262
Log:
Fix for a nasty bug in loading an fp reg with zero - thanks J!
Modified:
trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
Modified: trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-12-01 19:03:50=
UTC (rev 5261)
+++ trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-12-01 19:05:41=
UTC (rev 5262)
@@ -163,8 +163,8 @@
stw 3,28(1) /* spill orig guest_state ptr */
=20
/* 24(sp) used later to stop ctr reg being clobbered */
-
- /* 8:20(sp) free */
+ /* 20(sp) used later to load fpscr with zero */
+ /* 8:16(sp) free */
=09
/* Linkage Area (reserved)
4(sp) : LR
@@ -190,7 +190,14 @@
cmplwi 3,0
beq LafterFP2
=20
- fsub 3,3,3 /* generate zero */
+ /* get zero into f3 (tedious) */
+ /* note: fsub 3,3,3 is not a reliable way to do this,=20
+ since if f3 holds a NaN or similar then we don't necessarily
+ wind up with zero. */
+ li 3,0
+ stw 3,20(1)
+ lfs 3,20(1)
+ /* load f3 to fpscr (0xFF =3D all bit fields) */
mtfsf 0xFF,3
LafterFP2:
=20
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