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From: <sv...@va...> - 2005-11-16 20:22:16
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Author: cerion
Date: 2005-11-16 20:22:11 +0000 (Wed, 16 Nov 2005)
New Revision: 5155
Log:
Implemented checks for FPSCR and VSCR on leaving dispatcher
- required flags: FPSCR[RM] =3D=3D 0, VSCR[NJ] =3D=3D 1
Modified:
trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
Modified: trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-11-16 20:12:22=
UTC (rev 5154)
+++ trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-11-16 20:22:11=
UTC (rev 5155)
@@ -152,10 +152,12 @@
=20
/* Save cr */
mfcr 0
- stw 0,32(1)
+ stw 0,44(1)
=20
/* Local variable space... */
=20
+ /* 32(sp) used later to check FPSCR[RM] */
+
/* r3 holds guest_state */
mr 31,3
stw 3,28(1) /* spill orig guest_state ptr */
@@ -288,23 +290,43 @@
*/
run_innerloop_exit:=20
/* We're leaving. Check that nobody messed with
- %mxcsr or %fpucw. We can't mess with %eax here as it
- holds the tentative return value, but any other is OK. */
-// CAB: TODO
-=09
-//.. pushl $0
-//.. fstcw (%esp)
-//.. cmpl $0x027F, (%esp)
-//.. popl %esi /* get rid of the word without trashing %eflags */
-//.. jnz invariant_violation
+ VSCR or FPSCR. */
=20
-//.. pushl $0
-//.. stmxcsr (%esp)
-//.. andl $0xFFFFFFC0, (%esp) /* mask out status flags */
-//.. cmpl $0x1F80, (%esp)
-//.. popl %esi
-//.. jnz invariant_violation
-=09
+ /* Using r10 - value used again further on, so don't trash! */
+ lis 10,VG_(machine_ppc32_has_FP)@ha
+ lwz 10,VG_(machine_ppc32_has_FP)@l(10)
+ cmplwi 10,0
+ beq LafterFP8
+
+ /* Check FPSCR[RM] =3D=3D 0 */
+ mffs 4 /* fpscr -> fpr */
+ li 5,48
+ stfiwx 4,5,1 /* fpr to stack */
+ lwzx 6,5,1 /* load to gpr */
+ andi. 6,6,0x3 /* mask wanted bits */
+ cmplwi 6,0x0 /* cmp with zero */
+ bne invariant_violation /* branch if not zero */
+LafterFP8:
+
+ /* Using r11 - value used again further on, so don't trash! */
+ lis 11,VG_(machine_ppc32_has_VMX)@ha
+ lwz 11,VG_(machine_ppc32_has_VMX)@l(11)
+ cmplwi 11,0
+ beq LafterVMX8
+
+ /* Check VSCR[NJ] =3D=3D 1 */
+ /* first generate 4x 0x00010000 */
+ vspltisw 4,0x1 /* 4x 0x00000001 */
+ vspltisw 5,0x0 /* zero */
+ vsldoi 6,4,5,0x2 /* << 2bytes =3D> 4x 0x0001000=
0 */
+ /* retrieve VSCR and mask wanted bits */
+ mfvscr 7
+ vand 7,7,6 /* gives SAT flag */
+ vspltw 7,7,0x3 /* flags-word to all lanes */
+ vcmpequw. 8,6,7 /* CR[24] =3D 1 if equal */
+ bt 26,invariant_violation /* branch if bit 26 of CR is t=
rue */
+LafterVMX8:
+
/* otherwise we're OK */
b run_innerloop_exit_REALLY
=20
@@ -325,15 +347,13 @@
stw 17,VG_(dispatch_ctr)@l(18)
=20
/* Restore cr */
- lwz 0,32(1)
+ lwz 0,44(1)
mtcr 0
=20
/* Restore callee-saved registers... */
=20
- /* must use r4 since r3 holds return value */
- lis 4,VG_(machine_ppc32_has_FP)@ha
- lwz 4,VG_(machine_ppc32_has_FP)@l(4)
- cmplwi 4,0
+ /* r10 already holds VG_(machine_ppc32_has_FP) value */
+ cmplwi 10,0
beq LafterFP9
=20
/* Floating-point regs */
@@ -378,10 +398,8 @@
lwz 14,280(1)
lwz 13,276(1)
=20
- /* must use r4 since r3 holds return value */
- lis 4,VG_(machine_ppc32_has_VMX)@ha
- lwz 4,VG_(machine_ppc32_has_VMX)@l(4)
- cmplwi 4,0
+ /* r11 already holds VG_(machine_ppc32_has_VMX) value */
+ cmplwi 11,0
beq LafterVMX9
=20
/* VRSAVE */
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From: Cerion Armour-B. <ce...@op...> - 2005-11-16 20:29:45
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On Wednesday 16 November 2005 21:22, sv...@va... wrote: > Author: cerion > Date: 2005-11-16 20:22:11 +0000 (Wed, 16 Nov 2005) > New Revision: 5155 > > Log: > Implemented checks for FPSCR and VSCR on leaving dispatcher > - required flags: FPSCR[RM] == 0, VSCR[NJ] == 1 Can anyone tell me if I'm doing the right thing here, setting Non-Java mode to 1 in the dispatcher? I don't like the sound of the hack used (denormalised fp's set to zero), but it seems to be the default setting, at least on my system (PPC970FX). Cheers, Cerion |