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From: <sv...@va...> - 2005-11-10 18:11:04
|
Author: sewardj
Date: 2005-11-10 18:10:58 +0000 (Thu, 10 Nov 2005)
New Revision: 1449
Log:
Handle instrumentation artefacts arising from memchecking Altivec
code. Also, rename a few primops and add another folding rule.
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
trunk/priv/ir/irdefs.c
trunk/priv/ir/iropt.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-11-09 21:34:20 UTC (rev 1448)
+++ trunk/priv/guest-ppc32/toIR.c 2005-11-10 18:10:58 UTC (rev 1449)
@@ -6077,7 +6077,7 @@
assign( zHi, binop(Iop_Add32x4,
binop(Iop_MullEven16Ux8, mkexpr(aHi), mkexpr(bH=
i) ),
mkexpr(cHi)) );
- putVReg( vD_addr, binop(Iop_Narrow32Ux4, mkexpr(zHi), mkexpr(zLo))=
);
+ putVReg( vD_addr, binop(Iop_Narrow32x4, mkexpr(zHi), mkexpr(zLo)) =
);
break;
}
=20
@@ -6234,17 +6234,17 @@
/* Rotate */
case 0x004: // vrlb (Rotate Left Integer B, AV p234)
DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Rotl8x16, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_Rol8x16, mkexpr(vA), mkexpr(vB)) );
break;
=20
case 0x044: // vrlh (Rotate Left Integer HW, AV p235)
DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Rotl16x8, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_Rol16x8, mkexpr(vA), mkexpr(vB)) );
break;
=20
case 0x084: // vrlw (Rotate Left Integer W, AV p236)
DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Rotl32x4, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_Rol32x4, mkexpr(vA), mkexpr(vB)) );
break;
=20
=20
@@ -6546,12 +6546,12 @@
/* Packing */
case 0x00E: // vpkuhum (Pack Unsigned HW Unsigned Modulo, AV p224)
DIP("vpkuhum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Narrow16Ux8, mkexpr(vA), mkexpr(vB)) )=
;
+ putVReg( vD_addr, binop(Iop_Narrow16x8, mkexpr(vA), mkexpr(vB)) );
return True;
=20
case 0x04E: // vpkuwum (Pack Unsigned W Unsigned Modulo, AV p226)
DIP("vpkuwum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Narrow32Ux4, mkexpr(vA), mkexpr(vB)) )=
;
+ putVReg( vD_addr, binop(Iop_Narrow32x4, mkexpr(vA), mkexpr(vB)) );
return True;
=20
case 0x08E: // vpkuhus (Pack Unsigned HW Unsigned Saturate, AV p225)
@@ -6654,7 +6654,7 @@
assign( b_tmp, binop(Iop_OrV128, mkexpr(b1),
binop(Iop_OrV128, mkexpr(b2), mkexpr(b3))) );
=20
- putVReg( vD_addr, binop(Iop_Narrow32Ux4,
+ putVReg( vD_addr, binop(Iop_Narrow32x4,
mkexpr(a_tmp), mkexpr(b_tmp)) );
return True;
}
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-11-09 21:34:20 UTC (rev 1448)
+++ trunk/priv/host-ppc32/isel.c 2005-11-10 18:10:58 UTC (rev 1449)
@@ -2460,6 +2460,22 @@
return;
}
=20
+ case Iop_Neg64: {
+ HReg yLo, yHi;
+ HReg zero =3D newVRegI(env);
+ HReg tLo =3D newVRegI(env);
+ HReg tHi =3D newVRegI(env);
+ iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
+ addInstr(env, PPC32Instr_LI32(zero, 0));
+ addInstr(env, PPC32Instr_AddSubC32( False/*sub*/, True /*set=
carry*/,
+ tLo, zero, yLo));
+ addInstr(env, PPC32Instr_AddSubC32( False/*sub*/, False/*rea=
d carry*/,
+ tHi, zero, yHi));
+ *rHi =3D tHi;
+ *rLo =3D tLo;
+ return;
+ }
+
//.. /* Not64(e) */
//.. case Iop_Not64: {
//.. HReg tLo =3D newVRegI(env);
@@ -3000,6 +3016,27 @@
addInstr(env, PPC32Instr_AvUnary(Pav_NOT, dst, dst));
return dst;
}
+
+ case Iop_CmpNEZ16x8: {
+ HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
+ HReg zero =3D newVRegV(env);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBinary(Pav_XOR, zero, zero, zero));
+ addInstr(env, PPC32Instr_AvBin16x8(Pav_CMPEQU, dst, arg, zero))=
;
+ addInstr(env, PPC32Instr_AvUnary(Pav_NOT, dst, dst));
+ return dst;
+ }
+
+ case Iop_CmpNEZ32x4: {
+ HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
+ HReg zero =3D newVRegV(env);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBinary(Pav_XOR, zero, zero, zero));
+ addInstr(env, PPC32Instr_AvBin32x4(Pav_CMPEQU, dst, arg, zero))=
;
+ addInstr(env, PPC32Instr_AvUnary(Pav_NOT, dst, dst));
+ return dst;
+ }
+
//.. case Iop_CmpNEZ16x8: {
//.. /* We can use SSE2 instructions for this. */
//.. HReg arg;
@@ -3292,7 +3329,7 @@
case Iop_Shl8x16: op =3D Pav_SHL; goto do_AvBin8x16;
case Iop_Shr8x16: op =3D Pav_SHR; goto do_AvBin8x16;
case Iop_Sar8x16: op =3D Pav_SAR; goto do_AvBin8x16;
- case Iop_Rotl8x16: op =3D Pav_ROTL; goto do_AvBin8x16;
+ case Iop_Rol8x16: op =3D Pav_ROTL; goto do_AvBin8x16;
case Iop_InterleaveHI8x16: op =3D Pav_MRGHI; goto do_AvBin8x16;
case Iop_InterleaveLO8x16: op =3D Pav_MRGLO; goto do_AvBin8x16;
case Iop_Add8x16: op =3D Pav_ADDU; goto do_AvBin8x16;
@@ -3323,8 +3360,8 @@
case Iop_Shl16x8: op =3D Pav_SHL; goto do_AvBin16x8;
case Iop_Shr16x8: op =3D Pav_SHR; goto do_AvBin16x8;
case Iop_Sar16x8: op =3D Pav_SAR; goto do_AvBin16x8;
- case Iop_Rotl16x8: op =3D Pav_ROTL; goto do_AvBin16x8;
- case Iop_Narrow16Ux8: op =3D Pav_PACKUU; goto do_AvBin16x8;
+ case Iop_Rol16x8: op =3D Pav_ROTL; goto do_AvBin16x8;
+ case Iop_Narrow16x8: op =3D Pav_PACKUU; goto do_AvBin16x8;
case Iop_QNarrow16Ux8: op =3D Pav_QPACKUU; goto do_AvBin16x8;
case Iop_QNarrow16Sx8: op =3D Pav_QPACKSS; goto do_AvBin16x8;
case Iop_InterleaveHI16x8: op =3D Pav_MRGHI; goto do_AvBin16x8;
@@ -3357,8 +3394,8 @@
case Iop_Shl32x4: op =3D Pav_SHL; goto do_AvBin32x4;
case Iop_Shr32x4: op =3D Pav_SHR; goto do_AvBin32x4;
case Iop_Sar32x4: op =3D Pav_SAR; goto do_AvBin32x4;
- case Iop_Rotl32x4: op =3D Pav_ROTL; goto do_AvBin32x4;
- case Iop_Narrow32Ux4: op =3D Pav_PACKUU; goto do_AvBin32x4;
+ case Iop_Rol32x4: op =3D Pav_ROTL; goto do_AvBin32x4;
+ case Iop_Narrow32x4: op =3D Pav_PACKUU; goto do_AvBin32x4;
case Iop_QNarrow32Ux4: op =3D Pav_QPACKUU; goto do_AvBin32x4;
case Iop_QNarrow32Sx4: op =3D Pav_QPACKSS; goto do_AvBin32x4;
case Iop_InterleaveHI32x4: op =3D Pav_MRGHI; goto do_AvBin32x4;
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2005-11-09 21:34:20 UTC (rev 1448)
+++ trunk/priv/ir/irdefs.c 2005-11-10 18:10:58 UTC (rev 1449)
@@ -504,12 +504,12 @@
case Iop_Sar8x16: vex_printf("Sar8x16"); return;
case Iop_Sar16x8: vex_printf("Sar16x8"); return;
case Iop_Sar32x4: vex_printf("Sar32x4"); return;
- case Iop_Rotl8x16: vex_printf("Rotl8x16"); return;
- case Iop_Rotl16x8: vex_printf("Rotl16x8"); return;
- case Iop_Rotl32x4: vex_printf("Rotl32x4"); return;
+ case Iop_Rol8x16: vex_printf("Rol8x16"); return;
+ case Iop_Rol16x8: vex_printf("Rol16x8"); return;
+ case Iop_Rol32x4: vex_printf("Rol32x4"); return;
=20
- case Iop_Narrow16Ux8: vex_printf("Narrow16Ux8"); return;
- case Iop_Narrow32Ux4: vex_printf("Narrow32Ux4"); return;
+ case Iop_Narrow16x8: vex_printf("Narrow16x8"); return;
+ case Iop_Narrow32x4: vex_printf("Narrow32x4"); return;
case Iop_QNarrow16Ux8: vex_printf("QNarrow16Ux8"); return;
case Iop_QNarrow32Ux4: vex_printf("QNarrow32Ux4"); return;
case Iop_QNarrow16Sx8: vex_printf("QNarrow16Sx8"); return;
@@ -1575,10 +1575,10 @@
case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4:
case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4:
case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4:
- case Iop_Rotl8x16: case Iop_Rotl16x8: case Iop_Rotl32x4:
+ case Iop_Rol8x16: case Iop_Rol16x8: case Iop_Rol32x4:
case Iop_QNarrow16Ux8: case Iop_QNarrow32Ux4:
case Iop_QNarrow16Sx8: case Iop_QNarrow32Sx4:
- case Iop_Narrow16Ux8: case Iop_Narrow32Ux4:
+ case Iop_Narrow16x8: case Iop_Narrow32x4:
case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8:
case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2:
case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8:=20
Modified: trunk/priv/ir/iropt.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/iropt.c 2005-11-09 21:34:20 UTC (rev 1448)
+++ trunk/priv/ir/iropt.c 2005-11-10 18:10:58 UTC (rev 1449)
@@ -904,6 +904,11 @@
? 1 : 0));
break;
=20
+ case Iop_1Sto8:
+ e2 =3D IRExpr_Const(IRConst_U8(toUChar(
+ e->Iex.Unop.arg->Iex.Const.con->Ico.U1
+ ? 0xFF : 0)));
+ break;
case Iop_1Sto16:
e2 =3D IRExpr_Const(IRConst_U16(toUShort(
e->Iex.Unop.arg->Iex.Const.con->Ico.U1
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2005-11-09 21:34:20 UTC (rev 1448)
+++ trunk/pub/libvex_ir.h 2005-11-10 18:10:58 UTC (rev 1449)
@@ -581,12 +581,13 @@
Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4,
Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4,
Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4,
- Iop_Rotl8x16, Iop_Rotl16x8, Iop_Rotl32x4,
+ Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4,
=20
/* NARROWING -- narrow 2xV128 into 1xV128, hi half from left arg *=
/
+ /* Note: the 16{U,S} and 32{U,S} are the pre-narrow lane widths. *=
/
Iop_QNarrow16Ux8, Iop_QNarrow32Ux4,
Iop_QNarrow16Sx8, Iop_QNarrow32Sx4,
- Iop_Narrow16Ux8, Iop_Narrow32Ux4,
+ Iop_Narrow16x8, Iop_Narrow32x4,
=20
/* INTERLEAVING -- interleave lanes from low or high halves of
operands. Most-significant result lane is from the left
|