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From: <sv...@va...> - 2005-11-04 14:35:06
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Author: sewardj
Date: 2005-11-04 14:34:52 +0000 (Fri, 04 Nov 2005)
New Revision: 1433
Log:
Handle jecxz in addition to jrcxz.
Modified:
trunk/priv/guest-amd64/toIR.c
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-11-04 14:18:31 UTC (rev 1432)
+++ trunk/priv/guest-amd64/toIR.c 2005-11-04 14:34:52 UTC (rev 1433)
@@ -11635,19 +11635,30 @@
DIP("j%s-8 0x%llx\n", name_AMD64Condcode(opc - 0x70), d64);
break;
=20
- case 0xE3: /* JRCXZ or perhaps JECXZ, depending on OSO ? Intel
- manual says it depends on address size override,
- which doesn't sound right to me. But the amd manual
- alsay says that, so I guess it is. In which case 8
- is the only valid size. */
- if (have66orF2orF3(pfx) || haveASO(pfx)) goto decode_failure;
+ case 0xE3:=20
+ /* JRCXZ or JECXZ, depending address size override. */
+ if (have66orF2orF3(pfx)) goto decode_failure;
d64 =3D (guest_RIP_bbstart+delta+1) + getSDisp8(delta);=20
delta++;
- stmt( IRStmt_Exit( binop(Iop_CmpEQ64, getIReg64(R_RCX), mkU64(0)),
- Ijk_Boring,
- IRConst_U64(d64))=20
- );
- DIP("jrcxz 0x%llx\n", d64);
+ if (haveASO(pfx)) {
+ /* 32-bit */
+ stmt( IRStmt_Exit( binop(Iop_CmpEQ64,=20
+ unop(Iop_32Uto64, getIReg32(R_RCX)),=20
+ mkU64(0)),
+ Ijk_Boring,
+ IRConst_U64(d64))=20
+ );
+ DIP("jecxz 0x%llx\n", d64);
+ } else {
+ /* 64-bit */
+ stmt( IRStmt_Exit( binop(Iop_CmpEQ64,=20
+ getIReg64(R_RCX),=20
+ mkU64(0)),
+ Ijk_Boring,
+ IRConst_U64(d64))=20
+ );
+ DIP("jrcxz 0x%llx\n", d64);
+ }
break;
=20
case 0xE0: /* LOOPNE disp8: decrement count, jump if count !=3D 0 && =
ZF=3D=3D0 */
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